On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote: > Or: how to start a multicore (hyperthreading) processor as if it were > a singlecore (non-hyperthreading) processor. >
To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using the NetBurst Architecture. So SerialICE may need a patch for hyper-threaded CPUs to enable Cache-As-Ram, like coreboot does. You've seen my cache-as-ram code with SIPIs for model f25 (P4 Xeon on socket 604), to enable cache on HT-enabled CPU. >From your responses (on e-mail) so far, I cannot determine where (if) it stops with P4 models f29 and f49 on socket 478 (?). You have actual POST code PCI device, make wise use of it. Thanks, KM -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
