Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/639
-gerrit commit 1e27bae2f43c4ac137bc1b7cb4e9848f2981a45f Author: Kyösti Mälkki <[email protected]> Date: Thu Feb 16 11:05:55 2012 +0200 Intel cpus: use MAXPHYADDR from Kconfig during CAR This config determines the high 32 bits of MTRR mask registers as used during Cache-As-Ram. Run-time check in asm would be sort-of messy, but can be implemented at later time if found necessary. Default is MAXPHYADDR=36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <[email protected]> --- src/cpu/Kconfig | 7 +++++++ src/cpu/intel/model_106cx/Kconfig | 11 +++++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 3 +-- 5 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..d576873 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -19,6 +19,13 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x0 +config CPU_MAXPHYADDR + int + default 36 + help + Static CPU MAXPHYADDR used for MTRR mask during Cache-As-Ram. + Later MTRR setup uses run-time check with CPUID. + config MAX_PHYSICAL_CPUS int default 1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..fa6ebfd 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,17 @@ config CPU_INTEL_MODEL_106CX bool + +if CPU_INTEL_MODEL_106CX + +config CPU_SPECIFIC_OPTIONS # dummy + def_bool y select SMP select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + +config CPU_MAXPHYADDR + int + default 32 + +endif # CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..1e5ee64 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 32 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..a603472 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..9e3942b 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
