the following patch was just integrated into master:
commit ee068e84d951b1d198007371d767b920e82ba149
Author: Marc Jones <[email protected]>
Date: Mon Jan 30 19:30:45 2012 -0700
Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
The MTRR check for WB TOM2 setting was only checking revF, not extended
family
revisions. All families above revf indicate 0xf in the family field and have
additional bits in the extended family field.
Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f
Signed-off-by: Marc Jones <[email protected]>
Build-Tested: build bot (Jenkins) at Tue Feb 14 22:16:41 2012, giving +1
Reviewed-By: Stefan Reinauer <[email protected]> at Fri Feb 17
22:44:19 2012, giving +2
See http://review.coreboot.org/627 for details.
-gerrit
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