Frank Vibrans III ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/787
-gerrit commit e75774b6154c1ed5d19710364c4641c41672e5e2 Author: Frank Vibrans <[email protected]> Date: Tue Mar 13 10:57:49 2012 -0600 Union Station: Remove SIO support Because the Union Station platform doesn't have an SIO chip, this commit removes the Fintek SIO support. Change-Id: Idba4222ce136821dee2530a72d1630eb5ad613a2 Signed-off-by: Frank Vibrans <[email protected]> --- src/mainboard/amd/union_station/Kconfig | 1 - src/mainboard/amd/union_station/devicetree.cb | 24 ------------------------ src/mainboard/amd/union_station/romstage.c | 2 -- 3 files changed, 0 insertions(+), 27 deletions(-) diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index 194a39d..cc2e300 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F select BOARD_HAS_FADT select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index f0b471a..857bc02 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -56,30 +56,6 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f end #LPC device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 on end # USB 2 diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 26a05e8..f79e5ff 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,6 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" #include "cpu/x86/lapic/boot_cpu.c" #include "sb_cimx.h" #include "SBPLATFORM.h" @@ -55,7 +54,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
