Thanks for suggestions..I will go through the provided link. On Thu, Mar 15, 2012 at 11:12 PM, <[email protected]> wrote: > Send coreboot mailing list submissions to > [email protected] > > To subscribe or unsubscribe via the World Wide Web, visit > http://www.coreboot.org/mailman/listinfo/coreboot > or, via email, send a message with subject or body 'help' to > [email protected] > > You can reach the person managing the list at > [email protected] > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of coreboot digest..." > > > Today's Topics: > > 1. Patch merged into coreboot/master: a47f09d AGESA family 12 > changes to fix torpedo warnings ([email protected]) > 2. Re: SMP stop_this_cpu and AP_IN_SIPI_WAIT (ron minnich) > 3. Re: Problems with Winnet G270 Board / Igel Thin Client 3210 > need help (Christian) > 4. Patch merged into coreboot/master: 8cc685b Since cbfs_core.h > provides a macro that uses ntohl, make sure ntohl is available > ([email protected]) > 5. Fwd: kindly requesting to assign work on coreboot (manasa gv) > 6. Fwd: kindly requesting to assign work on coreboot (manasa gv) > 7. [RFC] Improve very early boot (Ky?sti M?lkki) > 8. Re: Fwd: kindly requesting to assign work on coreboot > (Paul Menzel) > 9. kindly requestig to assign work on coreboot (manasa gv) > 10. Re: [RFC] Improve very early boot (Patrick Georgi) > > > ---------------------------------------------------------------------- > > Message: 1 > Date: Wed, 14 Mar 2012 00:57:57 +0100 > From: [email protected] > To: [email protected] > Subject: [coreboot] Patch merged into coreboot/master: a47f09d AGESA > family 12 changes to fix torpedo warnings > Message-ID: <[email protected]> > Content-Type: text/plain; charset="UTF-8" > > the following patch was just integrated into master: > commit a47f09d8e723896eb63ae8437250c0ee7ce68da9 > Author: Martin Roth <[email protected]> > Date: Fri Feb 17 13:16:04 2012 -0700 > > AGESA family 12 changes to fix torpedo warnings > > Fixes the warnings generated in the torpedo mainboard build by AGESA. > Removing broken tests. > > Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b > Signed-off-by: Martin L Roth <[email protected]> > > Build-Tested: build bot (Jenkins) at Fri Feb 17 22:50:04 2012, giving +1 > Reviewed-By: Stefan Reinauer <[email protected]> at Wed Feb 29 > 23:32:35 2012, giving +2 > See http://review.coreboot.org/667 for details. > > -gerrit > > > > ------------------------------ > > Message: 2 > Date: Tue, 13 Mar 2012 19:40:41 -0700 > From: ron minnich <[email protected]> > To: Ky?sti M?lkki <[email protected]> > Cc: Coreboot <[email protected]> > Subject: Re: [coreboot] SMP stop_this_cpu and AP_IN_SIPI_WAIT > Message-ID: > > <cap6exyjzxny+8sxefkuw7pya_j_susvct1huf-iyb5hc70c...@mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > On Tue, Mar 13, 2012 at 1:13 PM, Ky?sti M?lkki <[email protected]> > wrote: > >> Seems like the patch just appeared and was merged without any >> discussion. It would have been nice to describe the circumstances under >> which Intel Core Duo failed... > > Assuming one is allowed to. Keep in mind that there are changes that > go in that people can't talk about because they are under some sort of > NDA. This may have been one of them. I do not know. > > ron > > > > ------------------------------ > > Message: 3 > Date: Wed, 14 Mar 2012 19:22:06 +0100 > From: Christian <[email protected]> > To: [email protected] > Subject: Re: [coreboot] Problems with Winnet G270 Board / Igel Thin > Client 3210 need help > Message-ID: <[email protected]> > Content-Type: text/plain; charset="UTF-8" > > >> >> For Via Model A Eden I have to change the >> >> static int c7a_speed_translation[] = { >> // LFM HFM > 0x0409, 0x0609 // 400MHz, 844mV --> 600MHz, 844mV Eden > insert this line for Via Eden 600MHz CPU >> 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V >> C7-M >> 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V >> 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V >> 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V >> 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V >> 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V >> 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V >> 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV >> C7-M ULV >> 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV >> 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV >> 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV >> }; > > I`m not sure about DRAM Frequency Loading the kernel is a little bit > slower as with factoy Bios, should be 266MHZ. > >> >> > > chris >> >> > > > > > > ------------------------------ > > Message: 4 > Date: Wed, 14 Mar 2012 23:00:27 +0100 > From: [email protected] > To: [email protected] > Subject: [coreboot] Patch merged into coreboot/master: 8cc685b Since > cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available > Message-ID: <[email protected]> > Content-Type: text/plain; charset="UTF-8" > > the following patch was just integrated into master: > commit 8cc685b2e006f3756dd26885b834fb198fa1f137 > Author: Gabe Black <[email protected]> > Date: Fri Sep 16 02:24:03 2011 -0700 > > Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available > > Since cbfs_core.h provides a macro that uses ntohl, make sure ntohl is > available by > including byteorder.h > > Change-Id: I9ab8cb51bd680e861b28d5130d09547bb9ab3b1f > Signed-off-by: Gabe Black <[email protected]> > > Build-Tested: build bot (Jenkins) at Fri Mar 9 05:43:36 2012, giving +1 > Reviewed-By: Peter Stuge <[email protected]> at Wed Mar 14 23:00:25 2012, > giving +2 > See http://review.coreboot.org/709 for details. > > -gerrit > > > > ------------------------------ > > Message: 5 > Date: Thu, 15 Mar 2012 15:39:31 +0530 > From: manasa gv <[email protected]> > To: [email protected] > Subject: [coreboot] Fwd: kindly requesting to assign work on coreboot > Message-ID: > > <calytimq4egnviwtxoh4etfz8hfv686hcb20bmfuqafkho5w...@mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > ---------- Forwarded message ---------- > From: manasa gv <[email protected]> > Date: Thu, Mar 15, 2012 at 3:27 PM > Subject: kindly requesting to assign work on coreboot > To: [email protected] > > > Respected sir, > > > I am Manasa, a graduate engineer intersted to work on > coreboot..I have gone through the coreboot website, flashrom,supported > mother boards,chipsets,bios savior and all those things.and also gone > through opencompute.org site to understand regarding mother board and bus > architecture..am new and interested to work on coreboot..so please > assign > some work related to coreboot.. > > > Regards & Thanks, > Manasa > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://www.coreboot.org/pipermail/coreboot/attachments/20120315/4e5df28f/attachment-0001.html> > > ------------------------------ > > Message: 6 > Date: Thu, 15 Mar 2012 16:46:30 +0430 > From: manasa gv <[email protected]> > To: [email protected], [email protected] > Subject: [coreboot] Fwd: kindly requesting to assign work on coreboot > Message-ID: > > <CALYtimraW8EU=oftut0+sxfx8sdrkye7gzyu4zpoxpf4chv...@mail.gmail.com> > Content-Type: text/plain; charset="iso-8859-1" > > ---------- Forwarded message ---------- > From: manasa gv <[email protected]> > Date: Thu, Mar 15, 2012 at 2:44 PM > Subject: Fwd: kindly requesting to assign work on coreboot > To: [email protected] > > > > > ---------- Forwarded message ---------- > From: manasa gv <[email protected]> > Date: Thu, Mar 15, 2012 at 3:39 PM > Subject: Fwd: kindly requesting to assign work on coreboot > To: [email protected] > > > > > ---------- Forwarded message ---------- > From: manasa gv <[email protected]> > Date: Thu, Mar 15, 2012 at 3:27 PM > Subject: kindly requesting to assign work on coreboot > To: [email protected] > > > Respected sir, > > > I am Manasa, a graduate engineer intersted to work on > coreboot..I have gone through the coreboot website, flashrom,supported > mother boards,chipsets,bios savior and all those things.and also gone > through opencompute.org site to understand regarding mother board and bus > architecture..am new and interested to work on coreboot..so please > assign > some work related to coreboot.. > > > Regards & Thanks, > Manasa > -------------- next part -------------- > An HTML attachment was scrubbed... > URL: > <http://www.coreboot.org/pipermail/coreboot/attachments/20120315/99fd96ca/attachment-0001.html> > > ------------------------------ > > Message: 7 > Date: Thu, 15 Mar 2012 16:00:49 +0200 > From: Ky?sti M?lkki <[email protected]> > To: Coreboot <[email protected]> > Subject: [coreboot] [RFC] Improve very early boot > Message-ID: <1331820049.1906.21.camel@obelix> > Content-Type: text/plain; charset="UTF-8" > > > Hi > > On selected boards, some hardware initialisation is placed in the > bootblock. The source files and directories are currently hard-coded in > Kconfigs, which is sort of ugly. > > A few months ago I put together changeset [1], which hasn't drawn much > review or interest. One benefit of my changeset is that it can be > extended to move superio and console initialisation to bootblock. > Serial-line IO can then be used to switch between fallback/normal > romstage and early POSTs could go to serial too. > > Thanks for any comments. > > KM > > [1] http://review.coreboot.org/#/c/473/ > > > > > > ------------------------------ > > Message: 8 > Date: Thu, 15 Mar 2012 15:40:02 +0100 > From: Paul Menzel <[email protected]> > To: [email protected] > Subject: Re: [coreboot] Fwd: kindly requesting to assign work on > coreboot > Message-ID: <1331822402.3718.35.camel@mattotaupa> > Content-Type: text/plain; charset="utf-8" > > Dear Manasa, > > > welcome and thank you very much for your interest in coreboot. I guess > your request is related to the Google Summer of Code program [2]? > > First of all, please read the netiquette [1] to learn best practice for > list communication (mailing list, no HTML messages, interleaved > quoting). > > > Am Donnerstag, den 15.03.2012, 16:46 +0430 schrieb manasa gv: > > [?] > >> I am Manasa, a graduate engineer intersted to work on >> coreboot..I have gone through the coreboot website, flashrom,supported >> mother boards,chipsets,bios savior and all those things.and also gone >> through opencompute.org site to understand regarding mother board and bus >> architecture..am new and interested to work on coreboot..so please >> assign >> some work related to coreboot.. > > There are several project proposals in the Wiki [3]. Best for you would > be to pick an area which interests you and start playing around to get > to know the code base. Do you already have coreboot running with Qemu? > > If you are undecided, you could do some patch review on Gerrit. > Especially patches > > 707, 606, 454, 644, 604, 607, 641, 643, 686 > > need testing and review. The following ones too. > > 709, 710 and 711 > > I would also very much like to see a payload like coreinfo letting you > change certain system setting like people are used to from a BIOS. > > > Thanks and I am looking forward to your contributions, > > Paul > > > [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette > [2] http://www.coreboot.org/GSoC > [3] http://www.coreboot.org/Project_Ideas > [4] http://review.coreboot.org/#/q/status:open,n,z > -------------- next part -------------- > A non-text attachment was scrubbed... > Name: signature.asc > Type: application/pgp-signature > Size: 198 bytes > Desc: This is a digitally signed message part > URL: > <http://www.coreboot.org/pipermail/coreboot/attachments/20120315/0f215039/attachment-0001.sig> > > ------------------------------ > > Message: 9 > Date: Thu, 15 Mar 2012 17:09:47 +0430 > From: manasa gv <[email protected]> > To: [email protected], [email protected] > Subject: [coreboot] kindly requestig to assign work on coreboot > Message-ID: > > <CALYtimqL2ObBH_eiKdjM=jqcyhgxxdtdpz6ssqelermf-jk...@mail.gmail.com> > Content-Type: text/plain; charset=ISO-8859-1 > > Respected sir, > > > ? ? ? ? ? ? ? I am Manasa, a graduate engineer intersted to work on > ? coreboot..I have gone through the coreboot website, flashrom,supported > ? mother boards,chipsets,bios savior and all those things.and also ?gone > ? through opencompute.org site to understand regarding mother board and > bus > ? architecture..am ?new and ?interested to work on coreboot..so please > assign > ? some work related to coreboot.. > > > ? Regards & Thanks, > ? Manasa > > > > ------------------------------ > > Message: 10 > Date: Thu, 15 Mar 2012 18:41:48 +0100 > From: Patrick Georgi <[email protected]> > To: [email protected] > Subject: Re: [coreboot] [RFC] Improve very early boot > Message-ID: <[email protected]> > Content-Type: text/plain; charset=ISO-8859-1 > > Am 15.03.2012 15:00, schrieb Ky?sti M?lkki: >> On selected boards, some hardware initialisation is placed in the >> bootblock. The source files and directories are currently hard-coded in >> Kconfigs, which is sort of ugly. >> >> A few months ago I put together changeset [1], which hasn't drawn much >> review or interest. > Thank you for that contribution - I'm really sorry that it fell through > the cracks. This was partly due to timing (slow development back then), > partly because it's a rather involved patch, doing similar things at once. > > It's not a very conscious decision on my part, but I sometimes look at > changes, and quickly close them because they overwhelm me, and I don't > always have the time and concentration to dive into it very deeply - > this one, I looked at several times, with no real results :-( > > I hereby pledge to resist that urge in the future and at least give some > hints on how I'd like to see things split up to simplify a review. > > Things that could be separated out: > - removing the AMD no-op bootblocks could be a separate change - that > probably would be committed in a day or two. > > - renaming the functions - I explicitely added the bootblock_ prefix so > the context in which this code is used is clear. It can be argued that > the filenames are enough of a clue, so that would probably go through as > well, after talking about this aspect. > > - the rest. It's a rather involved change. It doesn't turn coreboot > upside down, but I think it's much easier to consider the consequences > if we don't have to fear some side effect hidden in the "noise" of the > two changes above. > >> One benefit of my changeset is that it can be >> extended to move superio and console initialisation to bootblock. >> Serial-line IO can then be used to switch between fallback/normal >> romstage and early POSTs could go to serial too. > We can consider doing so (It adds complexity to something we tried to > keep small, but I think it's worth it). But we should also aim at moving > all chipsets to behave that way. > > You can't do that alone (of course), but a discussion on that on the > list (like what's going on now) goes a long way to make sure we all know > what to expect from the change, and to enlist support in making it > happen everywhere. > > > Thanks, > Patrick > > > > ------------------------------ > > _______________________________________________ > coreboot mailing list > [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot > > End of coreboot Digest, Vol 85, Issue 68 > ****************************************
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
