Patrick Georgi ([email protected]) just uploaded a new patch set to 
gerrit, which you can find at http://review.coreboot.org/444

-gerrit

commit 98907a679ecb191ab7f7d93d7c325079d9f69107
Author: Patrick Georgi <[email protected]>
Date:   Tue Nov 22 10:52:43 2011 +0100

    i82801gx: Support power-on-after-power-fail better
    
    Changing CMOS value for power-on-after-power-fail was only honored
    after reboot, which is counter intuitive (set from "enable" to "disable",
    power-off, replug device -> device turns on; and similar cases).
    
    Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
    Signed-off-by: Patrick Georgi <[email protected]>
---
 src/southbridge/intel/i82801gx/smihandler.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/southbridge/intel/i82801gx/smihandler.c 
b/src/southbridge/intel/i82801gx/smihandler.c
index 5cc25e7..401c9ad 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -316,16 +316,16 @@ static void southbridge_smi_sleep(unsigned int node, 
smm_state_save_area_t *stat
 
                outl(0, pmbase + GPE0_EN);
 
-               /* Should we keep the power state after a power loss?
-                * In case the setting is "ON" or "OFF" we don't have
-                * to do anything. But if it's "KEEP" we have to switch
-                * to "OFF" before entering S5.
+               /* Always set the flag in case CMOS was changed on runtime. For
+                * "KEEP", switch to "OFF" - KEEP is software emulated
                 */
-               if (s5pwr == MAINBOARD_POWER_KEEP) {
-                       reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), 
GEN_PMCON_3);
+               reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+               if (s5pwr == MAINBOARD_POWER_ON) {
+                       reg8 &= ~1;
+               } else {
                        reg8 |= 1;
-                       pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, 
reg8);
                }
+               pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 
                /* also iterates over all bridges on bus 0 */
                busmaster_disable_on_bus(0);

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