Hi Jullian On Sun, Mar 25, 2012 at 3:11 PM, Julian Shulika <[email protected]> wrote: > coreboot-4.0-2135-gccee625-dirty Fri Mar 23 15:02:04 EDT 2012 starting... > > BSP Family_Model: 00100f42 > > *sysinfo range: [000cc000,000cdfa0] > > bsp_apicid = 00 > cpu_init_detectedx = 00000000 > microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 > microcode: patch id to apply = 0x01000086 > microcode: updated to patch id = 0x01000086 success > > POST: 0x33 > cpuSetAMDMSR done > POST: 0x34 > Enter amd_ht_init() > AMD_CB_EventNotify() > event class: 05 > event: 1004 > data: 04 00 02 01 > AMD_CB_ManualBUIDSwapList() > AMD_CB_EventNotify() > event class: 05 > event: 2006 > data: 04 00 01 ff > Exit amd_ht_init() > POST: 0x35 > cpuSetAMDPCI 00 done > cpuSetAMDPCI 01 done > Prep FID/VID Node:00 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f24 > F3xD8: 03001615 > F3xDC: 00006322 > Prep FID/VID Node:01 > F3x80: e600e681 > F3x84: 80e641e6 > F3xD4: c3310f24 > F3xD8: 03001615 > F3xDC: 00006322 > setup_remote_node: 01 done > Start node 01 done. > POST: 0x36 > core0 started: POST: 0x30 > core0: --- { APICID = 04 NODEID = 01 COREID = 00} --- > 01microcode: equivalent rev id = 0x1041, current patch id = 0x00000000 > > itarmit_cortochoedr_e:c opreast(ch) > d to apply = 0x01000086 > iincriotc nooded:e: u0pd0a t ceodr teos : p0a3tc h > id = 0x01000086 success > > StcapurSt eottAhMDeMrS cRo re - nodeid: 00 cores: 03 > :nit dnoondee > ( 0i1 ni tc_ofriedsv:i d0_3a p > -stSatgaer1t) o atphiecri dco: re04 > s nFIoDdeVIiDd :o n0 1A P :c o0r4e > : 03 > POST: 0x37 > started ap apicid: PPPOOOSSSTTT::: 000xxx333000 > > > x cccooorrreeexxx::: --------- {{{ AAAPPPIIICCCIIIDDD === > 000132 NNNOOODDDEEEIIIDDD === 00x > > > * mAm33m3Pii00i0c ccrr0roo1occcooodddeee::: > eeeqqquuuiiivvvaaallleeennnttt rrreeevvv iiiddd === 0 > > > s > > > m tedmm > RE iciiccccocrrororroeorocecxcexoxoo: d:d:d e e e :-: :- - - -p-p-p-a a-at > t{t {c{cc Ah h hA P A iPiIiPIdIddCO > R > R > EIEIIDD D= == 0 10032}} }- -------- > > > tmmii*icc crrArmmmooPoiiiccc cccrroo0orooodd2dceccee::o:oodd d eueeuup:p::p > d dd eaeaeaqtqtqteueueuididdiv v a > t > t > h c > h > h > iiiddd === 000xxx000000000000000000000000 > > > AicAcMMapuuruSStSeeeemmdtmittiA > 6 McrorDDrDoMcoMMScSocSoRoRRde d d e:e:: p appaattcthcchh i iidd dt > ttoo oa aapppplppllyy y= = = 0 06 > > > u*mi iicAccrrPro ooc c0 cd3ooddododdoonnenee::ee:e > u > u > pppdddaaattteeeddd tttooo pppaaatttccchhh iiiddd === > 000xxx000111000000000000888666 sssuuucs > > > > > > AfAfMiipaipiunnurnuSSiiStietetteetdt_t__Af > MiMDDddDdMvMMvviSiSSiRdRddR _ _ _aaappp(((ssstttaaagggeee111))) > aaapppiiiccciiiddd::: 000123 > > > F*III DDDAVVVP III ddDDD0dooo 5nnnooonneeen > A > A > APPP::: 000123 > > > itiiiannnriiitttet__d_fff > iidddvvviiiddd___aaappp(((ssstttaaagggeee111))) aaapppiiiccciiiddd::: > 000657 > > > FFF*I IIDDADVVVPIII D0DD 6 ooonnn AAAPPP::: 000657 > > > started > * AP 07started > > POST: 0x38 > > Begin FIDVID MSR 0xc0010071 0x30b000a3 0x40034040 > POST: 0x39 > FIDVID on BSP, APIC_id: 00 > BSP fid = 10600 > Wait for AP stage 1: ap_apicid = 1 > readback = 1010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 2 > readback = 2010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 3 > readback = 3010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 4 > readback = 4010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 5 > readback = 5010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 6 > readback = 6010601 > common_fid(packed) = 10600 > Wait for AP stage 1: ap_apicid = 7 > readback = 7010601 > common_fid(packed) = 10600 > common_fid = 10600 > FID Change Node:00, F3xD4: c3310f26 > FID Change Node:01, F3xD4: c3310f26 > POST: 0x3a > End FIDVIDMSR 0xc0010071 0x30b000a3 0x30003040 > mcp55_num:01 > ...WARM RESET...
After the warm reset, coreboot should start again and get past the fid/vid setup and to the memory setup. Does it have a problem doing the warm reset? That could be a southbridge reset problem. marc -- http://se-eng.com -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
