Zheng Bao ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/621
-gerrit commit 667b587d3badf6f9134645115811372646638f59 Author: zbao <[email protected]> Date: Fri Mar 23 11:38:15 2012 +0800 Add Southbridge support for S3. 1. Add some CIMX call for S3. 2. Detect sleep type. Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9 Signed-off-by: Zheng Bao <[email protected]> Signed-off-by: zbao <[email protected]> --- src/southbridge/amd/cimx/sb800/cfg.c | 65 +++++++++++++++++++++++++++-- src/southbridge/amd/cimx/sb800/early.c | 8 ++++ src/southbridge/amd/cimx/sb800/late.c | 19 +++++++++ src/southbridge/amd/cimx/sb800/lpc.c | 4 +- src/southbridge/amd/cimx/sb800/lpc.h | 3 + src/southbridge/amd/cimx/sb800/sb_cimx.h | 4 ++ 6 files changed, 97 insertions(+), 6 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index a9e35bc..2a2ad2b 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -17,10 +17,63 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - +#include <console/console.h> #include "SBPLATFORM.h" #include "cfg.h" +#include <cbmem.h> + +#include <arch/io.h> +#include <arch/acpi.h> + +#define SB800_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB800_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB800_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (SB800_ACPI_IO_BASE + 0x0E) /* 1 byte */ +#define ACPI_PM_TMR_BLK (SB800_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB800_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB800_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); + return (int)tmp; +} +#endif + +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + +#ifndef __PRE_RAM__ +void set_cbmem_toc(struct cbmem_entry *toc) +{ + u32 dword = (u32) toc; + int nvram_pos = 0xf8, i; /* temp */ + printk(BIOS_DEBUG, "dword=%x\n", dword); + for (i = 0; i<4; i++) { + printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif +struct cbmem_entry *get_cbmem_toc(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (struct cbmem_entry *) xdata; +} /** * @brief South Bridge CIMx configuration @@ -30,10 +83,13 @@ */ void sb800_cimx_config(AMDSBCFG *sb_config) { - if (!sb_config) { + if (!sb_config) return; - } - //memset(sb_config, 0, sizeof(AMDSBCFG)); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_get_sleep_type() == 3) + sb_config->S3Resume = 1; +#endif /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; @@ -132,4 +188,3 @@ void sb800_cimx_config(AMDSBCFG *sb_config) } #endif //!__PRE_RAM__ } - diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 9d49a52..f692897 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -23,9 +23,11 @@ #include <device/pci_ids.h> #include <arch/io.h> /* inl, outl */ #include <arch/romcc_io.h> /* device_t */ +#include <arch/acpi.h> #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ +#include "cbmem.h" #if CONFIG_RAMINIT_SYSINFO == 1 @@ -80,3 +82,9 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } +#if CONFIG_HAVE_ACPI_RESUME == 1 +int acpi_is_wakeup_early(void) +{ + return (acpi_get_sleep_type() == 3); +} +#endif diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 8c7abdb..c69782b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,7 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <console/console.h> /* printk */ +#include <arch/acpi.h> #include "lpc.h" /* lpc_read_resources */ #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ @@ -351,6 +352,17 @@ void sb_Late_Post(void) AmdSbDispatcher(sb_config); } +void sb_Before_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} + +void sb_After_Pci_Restore_Init(void) +{ + sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; + AmdSbDispatcher(sb_config); +} /** * @brief SB Cimx entry point sbBeforePciInit wrapper @@ -468,7 +480,14 @@ static void sb800_enable(device_t dev) /* call the CIMX entry at the last sb800 device, * so make sure the mainboard devicetree is complete */ +#if CONFIG_HAVE_ACPI_RESUME == 1 + if (acpi_slp_type != 3) + sb_Before_Pci_Init(); + else + sb_Before_Pci_Restore_Init(); +#else sb_Before_Pci_Init(); +#endif break; default: diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c index bc643b5..472817d 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.c +++ b/src/southbridge/amd/cimx/sb800/lpc.c @@ -20,7 +20,9 @@ #include <console/console.h> #include <device/pci.h> #include "lpc.h" - +#include <bitops.h> +#include <arch/io.h> +#include <cbmem.h> void lpc_read_resources(device_t dev) { diff --git a/src/southbridge/amd/cimx/sb800/lpc.h b/src/southbridge/amd/cimx/sb800/lpc.h index 7b165f8..f6ffd53 100644 --- a/src/southbridge/amd/cimx/sb800/lpc.h +++ b/src/southbridge/amd/cimx/sb800/lpc.h @@ -21,6 +21,9 @@ #define _SB800_LPC_H_ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 + #define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */ void lpc_read_resources(device_t dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 42a7ba9..5e510de 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -29,6 +29,10 @@ void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); void sb_Mid_Post_Init(void); void sb_Late_Post(void); +void sb_Before_Pci_Restore_Init(void); +void sb_After_Pci_Restore_Init(void); + +int acpi_is_wakeup_early(void); /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
