Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/833
-gerrit commit dabe8452d2f6481597243b8c425645b2d3ce971a Author: Patrick Georgi <[email protected]> Date: Sat Mar 31 12:52:21 2012 +0200 Replace cache control magic numbers with symbols Instead of opaque numbers like (1<<29), use symbols like MTRRdefNoWriteThrough. Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5 Signed-off-by: Patrick Georgi <[email protected]> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/cpu/amd/car/disable_cache_as_ram.c | 2 +- src/cpu/intel/car/cache_as_ram.inc | 6 +++--- src/cpu/intel/car/cache_as_ram_ht.inc | 16 ++++++++-------- src/cpu/intel/model_106cx/cache_as_ram.inc | 14 +++++++------- src/cpu/intel/model_6ex/cache_as_ram.inc | 14 +++++++------- src/cpu/intel/model_6fx/cache_as_ram.inc | 14 +++++++------- src/cpu/via/car/cache_as_ram.inc | 8 ++++---- src/include/cpu/x86/mtrr.h | 2 ++ 9 files changed, 40 insertions(+), 38 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 4625da1..b0ad62b 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -320,7 +320,7 @@ wbcache_post_fam10_setup: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 jmp_if_k8(fam10_end_part1) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 0f91154..38edf63 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -26,7 +26,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) msr_t msr; /* disable cache */ - write_cr0(read_cr0() | (1 << 30)); + write_cr0(read_cr0() | MTRRdefCacheDisable); msr.lo = 0; msr.hi = 0; diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7742a68..60536b7 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -254,7 +254,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -328,7 +328,7 @@ lout: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 /* Clear sth. */ @@ -353,7 +353,7 @@ lout: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Clear boot_complete flag. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 2485e20..0d1b2a6 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -188,7 +188,7 @@ ap_init: /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 post_code(0x28) @@ -271,7 +271,7 @@ no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -284,7 +284,7 @@ no_msr_11e: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x2d) @@ -310,7 +310,7 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 post_code(0x2e) @@ -338,7 +338,7 @@ no_msr_11e: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x34) @@ -357,14 +357,14 @@ no_msr_11e: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x37) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -393,7 +393,7 @@ no_msr_11e: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..ca717ec 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -84,7 +84,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +98,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +122,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +150,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +181,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -207,7 +207,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..702ced5 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -84,7 +84,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -98,7 +98,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -122,7 +122,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -150,7 +150,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -181,14 +181,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -217,7 +217,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..e11c523 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -91,7 +91,7 @@ clear_mtrrs: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax invd movl %eax, %cr0 @@ -105,7 +105,7 @@ clear_mtrrs: /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 #if CONFIG_XIP_ROM_SIZE @@ -129,7 +129,7 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Set up the stack pointer. */ @@ -157,7 +157,7 @@ clear_mtrrs: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x31) @@ -188,14 +188,14 @@ clear_mtrrs: /* Enable cache. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x36) /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 post_code(0x38) @@ -214,7 +214,7 @@ clear_mtrrs: /* And enable cache again after setting MTRRs. */ movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax + andl $~(MTRRdefCacheDisable | MTRRdefNoWriteThrough), %eax movl %eax, %cr0 post_code(0x3a) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 90e6d2b..26b55e6 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -39,7 +39,7 @@ CacheAsRam: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 invd @@ -139,7 +139,7 @@ clear_fixed_var_mtrr_out: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 /* Read the range with lodsl. */ @@ -219,7 +219,7 @@ testok: /* Disable cache. */ movl %cr0, %eax - orl $(1 << 30), %eax + orl $MTRRdefCacheDisable, %eax movl %eax, %cr0 /* Set the default memory type and enable variable MTRRs. */ @@ -259,7 +259,7 @@ testok: /* Enable cache. */ movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax + andl $(~(MTRRdefCacheDisable | MTRRdefNoWriteThrough)), %eax movl %eax, %cr0 invd diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 8b5cc28..1299a9e 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -14,6 +14,8 @@ #define MTRRcap_MSR 0x0fe #define MTRRdefType_MSR 0x2ff +#define MTRRdefCacheDisable (1 << 30) +#define MTRRdefNoWriteThrough (1 << 29) #define MTRRdefTypeEn (1 << 11) #define MTRRdefTypeFixEn (1 << 10) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
