I'm not sure why it would be breaking anything, but it just doesn't make sense. From Volume 3: "Because all internal cache lines are invalid following reset initialization, it is not necessary to invalidate the cache before enabling caching." It is pretty weird, I downloaded one random Sandybridge ROM image from ECS, and I did not see the WBINVD before the far jmp.
Also, caches *should* remain valid after INIT, but this change will invalidate them unconditionally (unless INIT follows a different path in coreboot) Tom On Fri, Apr 6, 2012 at 11:26 AM, Stefan Reinauer <stefan.reina...@coreboot.org> wrote: > * Patrick Georgi <patr...@georgi-clan.de> [120406 17:32]: >> Am 06.04.2012 17:27, schrieb Marc Jones: >> > Can you be more descriptive to how it fails? Does it hang on that >> > instruction? >> That change might also break on future CPUs (if they finally manage >> to make the TPM stuff secure, so that's a big if) > > How so? > > Guess I'll have to work making that a CONFIG option. > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot