Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/964
-gerrit commit 887793df39d78bcdab65cb965a98fcd31b88fca4 Author: Gabe Black <[email protected]> Date: Thu Mar 29 17:58:52 2012 -0700 Set up the Emerald Lake 2 SMI and SCI sources based on the schematic. This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my best interpretation of the schematic. It may not be correct, but it doesn't seem to cause any problems either. Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97 Signed-off-by: Gabe Black <[email protected]> --- src/mainboard/intel/emeraldlake2/devicetree.cb | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 2631cfc..686fe2e 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -45,8 +45,10 @@ chip northbridge/intel/sandybridge # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi1_routing" = "0" + register "gpi1_routing" = "1" register "gpi14_routing" = "2" + register "alt_gp_smi_en" = "0x0002" + register "gpe0_en" = "0x4000" register "ide_legacy_combined" = "0x0" register "sata_ahci" = "0x1" -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
