Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/995
-gerrit commit cb60b660540716f4b6671e2b5d21bf75ec9c55e3 Author: Stefan Reinauer <[email protected]> Date: Wed May 2 16:39:56 2012 -0700 Don't pre-enable SATA AHCI in romstage.c In a recent commit the SATA code of Panther Point / Cougar Point was changed to enable AHCI mode depending on the device tree settings rather than a hard code hidden in romstage.c. However, Emerald Lake 2 was not fixed up accordingly. Change-Id: I6c93f386509361e1ab5565b0e4d0e84f0ba282a2 Signed-off-by: Stefan Reinauer <[email protected]> --- src/mainboard/intel/emeraldlake2/romstage.c | 3 --- 1 files changed, 0 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 879756b..aba89d4 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -132,9 +132,6 @@ static void early_pch_init(void) reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); reg8 &= ~(1 << 2); pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); - - // SATA - enable AHCI - pci_write_config16(PCH_SATA_DEV, 0x90, 0x0060); } static void setup_sio_gpios(void) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
