Denis Carikli ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1058
-gerrit commit 36c386f5387d0726be59db2193edd62cb3880136 Author: Denis 'GNUtoo' Carikli <[email protected]> Date: Sat May 26 00:13:22 2012 +0200 Fix the location of "Setting variable MTRR" printk. Without that fix the debugging is harder because the person debugging coreboot will see the following twice(note the repeated MTRR number): Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 4096MB, range: 512MB, type WB Setting variable MTRR 1, base: 4608MB, range: 256MB, type WB Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC instead of the following twice: Setting variable MTRR 0, base: 0MB, range: 4096MB, type WB [...] Setting variable MTRR 1, base: 3072MB, range: 1024MB, type UC Thanks to kmalkki on #coreboot's Freenode IRC channel for the idea: May 25 23:57:17 <kmalkki> I would add (move) that "Setting variable MTRR..." debug at the end of set_var_mtrrs() Change-Id: I9f4b7110ba34d017a58d8cc5fb06a7b1c3d0c8aa Signed-off-by: Denis 'GNUtoo' Carikli <[email protected]> --- src/cpu/x86/mtrr/mtrr.c | 11 ++++++----- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index cce526a..f8b2591 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -140,6 +140,12 @@ static void set_var_mtrr( wrmsr (MTRRphysMask_MSR(reg), mask); enable_cache(); + + printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", + reg, basek >>10, sizek >> 10, + (type==MTRR_TYPE_UNCACHEABLE)?"UC": + ((type==MTRR_TYPE_WRBACK)?"WB":"Other") + ); } /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ @@ -284,11 +290,6 @@ static unsigned int range_to_mtrr(unsigned int reg, align = max_align; } sizek = 1 << align; - printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", - reg, range_startk >>10, sizek >> 10, - (type==MTRR_TYPE_UNCACHEABLE)?"UC": - ((type==MTRR_TYPE_WRBACK)?"WB":"Other") - ); /* if range is above 4GB, MTRR is needed * only if above4gb flag is set -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
