diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 0ce82b3..34cd937 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -29,6 +29,7 @@
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
+#include "smbus.h"
 #include "sb_cimx.h"		/* AMD CIMX wrapper entries */
 
 
@@ -273,6 +274,7 @@ static struct device_operations pci_ops = {
         .set_resources = pci_dev_set_resources,
         .enable_resources = pci_bus_enable_resources,
         .init = pci_init,
+        .enable = 0,
         .scan_bus = pci_scan_bridge,
         .reset_bus = pci_bus_reset,
         .ops_pci = &lops_pci,
@@ -295,7 +297,7 @@ struct device_operations bridge_ops = {
 	.reset_bus        = pci_bus_reset,
 	.ops_pci          = &lops_pci,
 };
-
+#if 0
 /* 0:15:0 PCIe PortA */
 static const struct pci_driver PORTA_driver __pci_driver = {
         .ops = &bridge_ops,
@@ -323,7 +325,7 @@ static const struct pci_driver PORTD_driver __pci_driver = {
         .vendor = PCI_VENDOR_ID_ATI,
         .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
 };
-
+#endif
 
 /**
  * South Bridge CIMx ramstage entry point wrapper.
@@ -377,6 +379,7 @@ static void sb800_enable(device_t dev)
 	switch (dev->path.pci.devfn) {
 	case (0x11 << 3) | 0: /* 0:11.0  SATA */
 		/* the first sb800 device */
+		abcfg_reg(0xc0, 0x1FF, 0x0F4);
 		sb800_cimx_config(sb_config);
 
 		if (dev->enabled) {
@@ -455,6 +458,11 @@ static void sb800_enable(device_t dev)
 			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
 		}
 		break;
+	case (0x15 << 3) | 1:
+	case (0x15 << 3) | 2:
+	case (0x15 << 3) | 3:
+		//abcfg_reg(0xc0, 0xF0, 0x00);
+		break;
 
 	case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
 		sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled;
@@ -480,6 +488,7 @@ static void sb800_enable(device_t dev)
 		/* call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
+		abcfg_reg(0xc0, 0x100, 0x100);
 #if CONFIG_HAVE_ACPI_RESUME
 		if (acpi_slp_type != 3)
 			sb_Before_Pci_Init();