Sven Schnelle ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1099
-gerrit commit bd563e66681569f8b010f43a2289aa9d82537ec3 Author: Sven Schnelle <[email protected]> Date: Sun Jun 10 19:03:36 2012 +0200 udelay: add missing bus frequency commit 5b6404e4195157eac8d97ae5bf30f45612109d57 ("Fix timer frequency detection on Sandybridge") reworked the udelay code, but didn't add the 333MHz FSB entry used on Model 15 Xeons. Change-Id: Ie34f9ae3703b64672625e7bf1b943654a7a5eaa6 Signed-off-by: Sven Schnelle <[email protected]> --- src/cpu/x86/lapic/apic_timer.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index bb6cca7..a4106d4 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -34,7 +34,7 @@ static int set_timer_fsb(void) { struct cpuinfo_x86 c; int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; - int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; + int core2_fsb[8] = { 266, 133, 200, 166, 333, 100, -1, -1 }; get_fms(&c, cpuid_eax(1)); if (c.x86 != 6) @@ -45,7 +45,7 @@ static int set_timer_fsb(void) case 0x1c: /* Atom */ timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; break; - case 0xf: /* Core 2*/ + case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
