Anton Kochkov ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1143
-gerrit commit ba08fd1e1d823ad64c37d7e3d50a796ffbf81b9d Author: Anton Kochkov <[email protected]> Date: Wed Jun 27 07:16:03 2012 +0400 libpayload: OHCI driver correct PCI BAR reading Correct registers base (PCI BAR) reading to be more specification friendly. Registers base only in [31-12] bits, all other proposed to be 0 but that not true for some motherboards. So adding mask to use only valid bits. Change-Id: I2e9a4997e016dab812ccfe654e966bc91d42a625 Signed-off-by: Anton Kochkov <[email protected]> --- payloads/libpayload/drivers/usb/ohci.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 2e22ecf..8a01cf2 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -111,7 +111,9 @@ ohci_init (pcidev_t addr) OHCI_INST (controller)->roothub = controller->devices[0]; controller->bus_address = addr; - controller->reg_base = pci_read_config32 (controller->bus_address, 0x10); // OHCI mandates MMIO, so bit 0 is clear + /* regarding OHCI spec, Appendix A, BAR_OCHI register description, Table A-4 + * BASE ADDRESS only [31-12] bits. All other usually 0, but not all */ + controller->reg_base = pci_read_config32 (controller->bus_address, 0x10) & 0xfffff000; // OHCI mandates MMIO, so bit 0 is clear OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); printf("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
