Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1217
-gerrit commit b8b5b1e535becc2ff11767dced0d2a875e4b763e Author: Kyösti Mälkki <[email protected]> Date: Tue Jul 10 13:10:24 2012 +0300 AMD: Fix GFXUMA with 4GB or more RAM Northbridge code incorrectly adjusted the last cacheable memory resource to accomodate room for UMA framebuffer. If system had 4GB or more memory that last resource is not below 4GB and not the one where UMA is located. There are three consequences: The last entry in coreboot memory table is reduced by uma_memory_size. Due the incorrect code in northbridge code state.tomk, end of last resource below 4GB, had not been adjusted. Incrementing that by uma_memory_size diverts a region possibly claimed for MMIO to RAM, as TOP_MEM is written. Since the UMA framebuffer did not have IORESOURCE_CACHEABLE, it was ignored from the MTRR setup and not set uncacheable. The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs, should be copied from BSP to all APs instead of deriving the data separately for each Logical CPU. Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/cpu/amd/mtrr/amd_mtrr.c | 24 ++++++++++++++----- src/northbridge/amd/agesa/family10/northbridge.c | 5 ---- src/northbridge/amd/agesa/family15/northbridge.c | 5 ---- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 ---- src/northbridge/amd/amdfam10/northbridge.c | 5 ---- src/northbridge/amd/amdk8/northbridge.c | 12 +-------- 6 files changed, 19 insertions(+), 37 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index ec72425..f639d59 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -102,6 +102,20 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc } +static void uma_fb_resource(void *gp, struct device *dev, struct resource *res) +{ + struct mem_state *state = gp; + unsigned long topk; + + topk = resk(res->base + res->size); + if (state->tom2k < topk) { + state->tom2k = topk; + } + if ((topk < 4*1024*1024) && (state->tomk < topk)) { + state->tomk = topk; + } +} + void amd_setup_mtrrs(void) { unsigned long address_bits; @@ -133,6 +147,9 @@ void amd_setup_mtrrs(void) state.tomk = state.tom2k = 0; search_global_resources( + IORESOURCE_MEM | IORESOURCE_UMA_FB, IORESOURCE_MEM | IORESOURCE_UMA_FB, + uma_fb_resource, &state); + search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, &state); @@ -144,13 +161,6 @@ void amd_setup_mtrrs(void) state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB; msr.hi = state.tomk >> 22; msr.lo = state.tomk << 10; - /* If UMA graphics is enabled, the frame buffer memory - * has been deducted from the size of memory below 4GB. - * When setting TOM, include UMA DRAM - */ - #if CONFIG_GFXUMA - msr.lo += uma_memory_size; - #endif wrmsr(TOP_MEM, msr); /* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */ diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 12d83ad..fb64757 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1063,11 +1063,6 @@ static void amdfam10_domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA - /* Deduct uma memory before reporting because - * this is what the mtrr code expects */ - sizek -= uma_memory_size / 1024; -#endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index d9da183..0e18956 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -782,11 +782,6 @@ static void domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA - /* Deduct uma memory before reporting because - * this is what the mtrr code expects */ - sizek -= uma_memory_size / 1024; -#endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index efc8e68..0330017 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -768,11 +768,6 @@ static void domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA == 1 - /* Deduct uma memory before reporting because - * this is what the mtrr code expects */ - sizek -= uma_memory_size / 1024; -#endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES==1 diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 41434e8..39b4a40 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1051,11 +1051,6 @@ static void amdfam10_domain_set_resources(device_t dev) } } -#if CONFIG_GFXUMA - /* Deduct uma memory before reporting because - * this is what the mtrr code expects */ - sizek -= uma_memory_size / 1024; -#endif ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 8b9140d..36dd2b4 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -1030,16 +1030,8 @@ static void amdk8_domain_set_resources(device_t dev) sizek -= (4*1024*1024 - mmio_basek); } } - /* If sizek == 0, it was split at mmio_basek without a hole. - * Don't create an empty ram_resource. - */ -#if CONFIG_GFXUMA - /* Deduct uma memory before reporting because - * this is what the mtrr code expects */ - sizek -= uma_memory_size / 1024; -#endif - if (sizek) - ram_resource(dev, (idx | i), basek, sizek); + + ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; #if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
