Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1330
-gerrit commit 93f232dad8f8e544153c14b6d57cb66395adb960 Author: Stefan Reinauer <[email protected]> Date: Tue Jul 10 13:24:29 2012 -0700 Fix LAPIC timer on Ivy Bridge systems The LAPIC timer is running at BCLK (100MHz) on Sandy Bridge and Ivy Bridge systems. However, the current timer code assumed that the clock would run at 200MHz instead. This made all delays twice as long as needed. Change-Id: I41b1186daee11cfd9a25b3a9d5ebdeeb271293c7 Signed-off-by: Stefan Reinauer <[email protected]> --- src/cpu/x86/lapic/apic_timer.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 1fd0c60..562c79c 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -50,6 +50,7 @@ static int set_timer_fsb(void) timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; break; case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ + case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ timer_fsb = 100; break; default: -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
