Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1340
-gerrit commit 13b65191bbcc97e2526c74cec03eba5f8e50d5fd Author: Duncan Laurie <[email protected]> Date: Mon Jul 16 11:28:52 2012 -0700 NVS: Add a temp sensor ID and an ACPI Method to set it This will allow various teams to select which thermal sensor will control the thermal zones. Also add a method to notify the thermalzones of a change so these threshold/sensor methods take effect. Needs a modified BIOS that uses the NVS TMPS value in the thermalzone to read a different sensor. Then, use a kernel driver that contains the following: /* Adjust temperature sensor id to 2 */ union acpi_object param; struct acpi_object_list input; param.type = ACPI_TYPE_INTEGER param.integer.value = 2 input.count = 1; input.pointer = ¶m; acpi_evaluate_object(NULL, "\\TMPU", &input, NULL); And ensure that the temperature sensor that is being monitored switches to ID 2. Change-Id: I6319741358ba31eb8a3dc635d64f3f0acf683386 Signed-off-by: Duncan Laurie <[email protected]> --- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 33 ++++++++++++++++++++- src/southbridge/intel/bd82x6x/nvs.h | 3 +- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index df450e3..7aeb32b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -71,6 +71,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) F4OF, 8, // 0x22 - FAN 4 OFF Threshold F4ON, 8, // 0x23 - FAN 4 ON Threshold F4PW, 8, // 0x24 - FAN 4 PWM value + TMPS, 8, // 0x25 - Temperature Sensor ID /* Processor Identification */ Offset (0x28), APIC, 8, // 0x28 - APIC Enabled by coreboot @@ -82,8 +83,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Super I/O & CMOS config */ Offset (0x32), NATP, 8, // 0x32 - - S5U0, 8, // 0x32 - Enable USB0 in S5 - S5U1, 8, // 0x33 - Enable USB1 in S5 + S5U0, 8, // 0x33 - Enable USB0 in S5 + S5U1, 8, // 0x34 - Enable USB1 in S5 S3U0, 8, // 0x35 - Enable USB0 in S3 S3U1, 8, // 0x36 - Enable USB1 in S3 S33G, 8, // 0x37 - Enable 3G in S3 @@ -208,11 +209,28 @@ Method (S3GD) Store (Zero, \S33G) } +External (\_TZ.THRM) +External (\_TZ.SKIN) + +Method (TZUP) +{ + /* Update Primary Thermal Zone */ + If (CondRefOf (\_TZ.THRM, Local0)) { + Notify (\_TZ.THRM, 0x81) + } + + /* Update Secondary Thermal Zone */ + If (CondRefOf (\_TZ.SKIN, Local0)) { + Notify (\_TZ.SKIN, 0x81) + } +} + /* Update Fan 0 thresholds */ Method (F0UT, 2) { Store (Arg0, \F0OF) Store (Arg1, \F0ON) + TZUP () } /* Update Fan 1 thresholds */ @@ -220,6 +238,7 @@ Method (F1UT, 2) { Store (Arg0, \F1OF) Store (Arg1, \F1ON) + TZUP () } /* Update Fan 2 thresholds */ @@ -227,6 +246,7 @@ Method (F2UT, 2) { Store (Arg0, \F2OF) Store (Arg1, \F2ON) + TZUP () } /* Update Fan 3 thresholds */ @@ -234,6 +254,7 @@ Method (F3UT, 2) { Store (Arg0, \F3OF) Store (Arg1, \F3ON) + TZUP () } /* Update Fan 4 thresholds */ @@ -241,4 +262,12 @@ Method (F4UT, 2) { Store (Arg0, \F4OF) Store (Arg1, \F4ON) + TZUP () +} + +/* Update Temperature Sensor ID */ +Method (TMPU, 1) +{ + Store (Arg0, \TMPS) + TZUP () } diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 3928804..2d94a64 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -55,7 +55,8 @@ typedef struct { u8 f4of; /* 0x22 - FAN 4 OFF Threshold */ u8 f4on; /* 0x23 - FAN 4 ON Threshold */ u8 f4pw; /* 0x24 - FAN 4 PWM value */ - u8 rsvd3[3]; + u8 tmps; /* 0x25 - Temperature Sensor ID */ + u8 rsvd3[2]; /* Processor Identification */ u8 apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
