Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1345
-gerrit commit 369ab60207dd36c3072ed86939143809bc7d6bae Author: Duncan Laurie <[email protected]> Date: Fri Jul 13 10:11:54 2012 -0700 Log event for abnormal management engine status This will log if the ME is disabled or has an error. 1) disable ME via EC console: gpioset PCH_HDA_SDO 1 2) boot the device 3) read eventlog with "mosys eventlog list" 71 | 2012-07-13 10:10:55 | Management Engine | Disabled Change-Id: I9f6ee452d2aea76e6a5ea2cd50a50ff36245692a Signed-off-by: Duncan Laurie <[email protected]> --- src/include/elog.h | 3 +++ src/southbridge/intel/bd82x6x/me.c | 7 ++++--- src/southbridge/intel/bd82x6x/me_8.x.c | 7 ++++--- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/src/include/elog.h b/src/include/elog.h index 7d89f45..5a84c75 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -105,6 +105,9 @@ struct elog_event_data_wake { #define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0 #define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1 +/* Management Engine Events */ +#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2 + extern int elog_init(void); extern int elog_clear(void); extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 464d0fd..3b7f342 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -727,9 +728,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } } diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 74bf1ae..9461d61 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -35,6 +35,7 @@ #include <device/pci_def.h> #include <string.h> #include <delay.h> +#include <elog.h> #ifdef __SMM__ # include <arch/romcc_io.h> @@ -730,9 +731,9 @@ static void intel_me_init(device_t dev) case ME_RECOVERY_BIOS_PATH: case ME_DISABLE_BIOS_PATH: case ME_FIRMWARE_UPDATE_BIOS_PATH: - /* - * TODO(dlaurie) Force recovery mode if ME is unhappy? - */ +#if CONFIG_ELOG + elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path); +#endif break; } } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
