Dave Frodin ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1475
-gerrit commit f9396968d7dfdd36288fc9eb33e0c97862bd83fc Author: Dave Frodin <[email protected]> Date: Tue Aug 21 16:51:33 2012 -0600 SB700/SP5100: This configures the HPET clock period. Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin <[email protected]> --- src/southbridge/amd/sb700/early_setup.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index c890ad9..648b0d9 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -420,6 +420,14 @@ static void sb700_devices_por_init(void) byte |= 0x24; pci_write_config8(dev, 0x62, byte); + /* Configure HPET Counter CLK period */ + byte = pci_read_config8(dev, 0x43); + byte &= 0xF7; /* unhide HPET regs */ + pci_write_config8(dev, 0x43, byte); + pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */ + byte |= 0x08; /* hide HPET regs */ + pci_write_config8(dev, 0x43, byte); + /* Features Enable */ pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
