Alexandru Gagniuc ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1463
-gerrit commit 1ad7faced8828af71149311519ae174598445587 Author: Sven Schnelle <[email protected]> Date: Mon Aug 20 11:22:37 2012 +0200 bd82x6x: remove ioapic initialization This now done by the generic ioapic driver. Change-Id: Iea648158c429ee5b053c7b3f3cdfcfaecb4eb4c3 Signed-off-by: Sven Schnelle <[email protected]> --- src/southbridge/intel/bd82x6x/lpc.c | 49 ++----------------------------------- 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592f5de..3a6140f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -26,7 +26,6 @@ #include <pc80/isa-dma.h> #include <pc80/i8259.h> #include <arch/io.h> -#include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/cpu.h> #include <elog.h> @@ -39,45 +38,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static void pch_enable_apic(struct device *dev) -{ - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 - */ - pci_write_config8(dev, ACPI_CNTL, 0x80); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - /* affirm full set of redirection table entries ("write once") */ - *ioapic_index = 1; - reg32 = *ioapic_data; - *ioapic_index = 1; - *ioapic_data = reg32; - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ -} - static void pch_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ @@ -537,8 +497,8 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); - /* IO APIC initialization. */ - pch_enable_apic(dev); + /* enable ACPI */ + pci_write_config8(dev, ACPI_CNTL, 0x80); pch_enable_serial_irqs(dev); @@ -612,11 +572,6 @@ static void pch_lpc_read_resources(device_t dev) res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, 3); /* IOAPIC */ - res->base = IO_APIC_ADDR; - res->size = 0x00001000; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Set PCH IO decode ranges if required.*/ if ((config->gen1_dec & 0xFFFC) > 0x1000) { res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
