Stefan Tauner ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1581
-gerrit commit f87b0084fb4ffad4cafb9df88a2e65e291b8e556 Author: Stefan Tauner <[email protected]> Date: Sat Oct 13 13:15:04 2012 +0200 Add support for socket LGA775 Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <[email protected]> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_LGA775/Kconfig | 28 ++++++++++++++++++++++++++++ src/cpu/intel/socket_LGA775/Makefile.inc | 17 +++++++++++++++++ src/cpu/intel/socket_LGA775/socket_LGA775.c | 5 +++++ 5 files changed, 52 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index c6dab12..c3cf4c9 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -30,4 +30,5 @@ source src/cpu/intel/socket_mPGA604/Kconfig source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA771/Kconfig +source src/cpu/intel/socket_LGA775/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 9e498f1..782c15a 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -20,6 +20,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 #socket_mPGA604_533Mhz #socket_mPGA604_800Mhz diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig new file mode 100644 index 0000000..dfb3181 --- /dev/null +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -0,0 +1,28 @@ +config CPU_INTEL_SOCKET_LGA775 + bool + +if CPU_INTEL_SOCKET_LGA775 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX + select CPU_INTEL_MODEL_F3X + select CPU_INTEL_MODEL_F4X +# select CPU_INTEL_MODEL_F6X +# select CPU_INTEL_MODEL_1066X + select CPU_INTEL_MODEL_1067X + select MMX + select SSE + select UDELAY_TSC + select SIPI_VECTOR_IN_ROM + +config DCACHE_RAM_SIZE + hex + default 0x4000 # 16 kB + +config DCACHE_RAM_BASE + hex + default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE + +endif # CPU_INTEL_SOCKET_LGA775 diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc new file mode 100644 index 0000000..100b4d8 --- /dev/null +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -0,0 +1,17 @@ +ramstage-y += socket_LGA775.c +subdirs-y += ../model_6ex +subdirs-y += ../model_6fx +subdirs-y += ../model_f3x +subdirs-y += ../model_f4x +#subdirs-y += ../model_f6x +#subdirs-y += ../model_1066x +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc diff --git a/src/cpu/intel/socket_LGA775/socket_LGA775.c b/src/cpu/intel/socket_LGA775/socket_LGA775.c new file mode 100644 index 0000000..7ec4e5e --- /dev/null +++ b/src/cpu/intel/socket_LGA775/socket_LGA775.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_LGA775_ops = { + CHIP_NAME("Socket LGA775 CPU") +}; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
