Siyuan Wang ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1594
-gerrit commit cf21f9dbe8b5607cf40056e9805b58025bcf48f2 Author: Siyuan Wang <[email protected]> Date: Tue Oct 23 14:14:46 2012 +0800 tyan s8226: move pcie training to romstage We move s8226's 2 cimx wrappers to romstage due to last commit. The changes are include Pcie_Early_Init and Pcie_Late_Init. In order to config rd890 in romstage, we modify rd890_cfg.c too. We find the rd890 in device list and get the config. Change-Id: I4ff70d0e6a0235b87806a64376f3ecee6487fdee Signed-off-by: Siyuan Wang <[email protected]> Signed-off-by: Siyuan Wang <[email protected]> --- src/mainboard/tyan/s8226/rd890_cfg.c | 78 ++---------------------------------- src/mainboard/tyan/s8226/rd890_cfg.h | 1 + src/mainboard/tyan/s8226/romstage.c | 10 +++++ 3 files changed, 14 insertions(+), 75 deletions(-) diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 7a947b3..79238a5 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -23,83 +23,13 @@ #include "nbInitializer.h" #include <string.h> #include <arch/ioapic.h> - -#ifndef __PRE_RAM__ #include <device/device.h> + +extern ROMSTAGE_CONST struct device dev_root; extern void set_pcie_reset(void *config); extern void set_pcie_dereset(void *config); /** - * Platform dependent configuration at ramstage - */ -static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) -{ - u16 i; - PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; - //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); - struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; - DEFAULT_PLATFORM_CONFIG(platform_config); - - /* update the platform depentent configuration by devicetree */ - rd890_info = nb_dev->chip_info; - platform_config.PortEnableMap = rd890_info->port_enable; - if (rd890_info->gpp1_configuration == 0) { - platform_config.Gpp1Config = GFX_CONFIG_AAAA; - } else if (rd890_info->gpp1_configuration == 1) { - platform_config.Gpp1Config = GFX_CONFIG_AABB; - } - if (rd890_info->gpp2_configuration == 0) { - platform_config.Gpp2Config = GFX_CONFIG_AAAA; - } else if (rd890_info->gpp2_configuration == 1) { - platform_config.Gpp2Config = GFX_CONFIG_AABB; - } - platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; - - if (platform_config.Gpp1Config != 0) { - pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; - } - if (platform_config.Gpp2Config != 0) { - pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; - } - if (platform_config.Gpp3aConfig != 0) { - pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; - } - - pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); - for (i = 0; i <= MAX_CORE_ID; i++) { - NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; - NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; - } - for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { - NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; - } - - for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { - if ((platform_config.PortEnableMap & (1 << i)) != 0) { - pPcieConfig->PortConfiguration[i].PortPresent = ON; - if ((platform_config.PortGen1Map & (1 << i)) != 0) { - pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; - } - if ((platform_config.PortHotplugMap & (1 << i)) != 0) { - u16 j; - pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ - /* Set Hotplug descriptor info */ - for (j = 0; j < 8; j++) { - u32 PortDescriptor; - PortDescriptor = platform_config.PortHotplugDescriptors[j]; - if ((PortDescriptor & 0xF) == j) { - pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; - pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; - break; - } - } - } - } - } -} -#endif // __PRE_RAM__ - -/** * @brief Entry point of Northbridge CIMx callout/CallBack * * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); @@ -160,9 +90,6 @@ static u32 rd890_callout_entry(u32 func, u32 data, void *config) break; case CB_AmdSetPcieEarlyConfig: -#ifndef __PRE_RAM__ - nb_platform_config(nb_dev, nbConfigPtr); -#endif break; case CB_AmdSetEarlyPostConfig: @@ -244,6 +171,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; //TODO: other NBs + pConfig->Northbridges[0].pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; #ifndef __PRE_RAM__ /* If temporrary MMIO enable set up CPU MMIO */ diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h index 8f45019..b11928f 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.h +++ b/src/mainboard/tyan/s8226/rd890_cfg.h @@ -170,5 +170,6 @@ typedef struct { * Bridge CIMx configuration */ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); +void nb_platform_config(AMD_NB_CONFIG_BLOCK *pConfigPtr); #endif //_RD890_CFG_H_ diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7076eed..f80d347 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -45,6 +45,10 @@ extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; post_code(0x30); agesawrapper_amdinitmmio(); @@ -139,6 +143,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x51); setup_i8259 (); setup_i8254 (); + + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + nb_pcie_config(&gConfig); + nb_Pcie_Early_Init(&gConfig); + nb_Pcie_Late_Init(&gConfig); + copy_and_run(0); /* We will not return, Should never see this message and post code. */ -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
