Zheng Bao ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1661
-gerrit commit 077606508bd958b2ac1da368743ac3062cf71b23 Author: Zheng Bao <[email protected]> Date: Thu Nov 1 17:53:04 2012 +0800 Supermicro h8qgi: Set the mask of MTRR to 0000FFFXX0000800 Tested by Aladyshev Konstantin, got from (http://review.coreboot.org/#/c/1349/) The high bits of mtrr mask are MBZ (Must be zero). Writing 1 to these bits will cause exception. So be carefull when spread this change. Which is the last bits that should be set? Can these be detect without writing 1 to high bit? Change-Id: I2dd8bf07ecee2fe4d1721cec6b21623556e68947 Signed-off-by: Zheng Bao <[email protected]> Signed-off-by: zbao <[email protected]> --- src/mainboard/supermicro/h8qgi/agesawrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index aeeab11..96dc2a6 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -194,7 +194,7 @@ UINT32 agesawrapper_amdinitmmio(VOID) /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + MsrReg = (0x1000000000000 - CONFIG_ROM_SIZE) | 0x800; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
