just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1681
-gerrit commit 73097097426edd10dd1032393f1eb2bf7d320112 Author: Siyuan Wang <[email protected]> Date: Fri Nov 2 18:14:30 2012 +0800 remove enable_cache() of 3 mainboards Because enable cache is added at the end of disable_cache_as_ram, ( http://review.coreboot.org/#/c/1662/2/src/cpu/amd/agesa/cache_as_ram.inc ) enable_cache() should be removed. The 3 mainboards are: amd parmer, amd thatcher and tyan s8226 Change-Id: If870ca07d2e97b9e860a2e2315f551251c7a4ed2 Signed-off-by: Siyuan Wang <[email protected]> Signed-off-by: Siyuan Wang <[email protected]> Reviewed-on: http://review.coreboot.org/1669 Reviewed-by: Marc Jones <[email protected]> Tested-by: build bot (Jenkins) --- src/mainboard/amd/parmer/romstage.c | 2 -- src/mainboard/amd/thatcher/romstage.c | 2 -- src/mainboard/tyan/s8226/romstage.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 028d6ae..56fcb57 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> #include <console/console.h> #include <console/loglevel.h> #include "agesawrapper.h" @@ -102,7 +101,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); - enable_cache(); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index f7ffa4e..e0cfd02 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <cpu/x86/cache.h> #include <console/console.h> #include <console/loglevel.h> #include "agesawrapper.h" @@ -119,7 +118,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n"); disable_cache_as_ram(); - enable_cache(); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 7076eed..c10176b 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -35,7 +35,6 @@ #include "superio/winbond/w83627dhg/w83627dhg.h" #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -#include <cpu/x86/cache.h> extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ @@ -133,7 +132,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); - enable_cache(); print_debug("done\n"); post_code(0x51); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
