Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1704
-gerrit commit a3106877b3cebf0483e1643447da4d46edc6ccc1 Author: Duncan Laurie <[email protected]> Date: Mon Aug 13 09:41:54 2012 -0700 SMI: Change order of SMI_EN and PM1_EN init This appears to fix an infrequent resume hang on Ivybridge. Tested on 2 devices with 15k suspend/resume cycles each Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473 Signed-off-by: Duncan Laurie <[email protected]> --- src/southbridge/intel/bd82x6x/smi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index bd4d32c..bd88df2 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -269,6 +269,11 @@ static void smm_relocate(void) gpe0_en &= ~PME_B0_EN; outl(gpe0_en, pmbase + GPE0_EN); + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) @@ -301,11 +306,6 @@ static void smm_relocate(void) outl(smi_en, pmbase + SMI_EN); - pm1_en = 0; - pm1_en |= PWRBTN_EN; - pm1_en |= GBL_EN; - outw(pm1_en, pmbase + PM1_EN); - /** * There are several methods of raising a controlled SMI# via * software, among them: -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
