Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1794
-gerrit commit 67ced73ab60f11289281984f3b812a675f517db1 Author: Marc Jones <[email protected]> Date: Thu Oct 25 14:01:37 2012 -0600 Initialize the VMX MSR The VMX MSR may come up with random values and needs to be initialized to zero. This was done incorrectly in finalize_smm. It must be done on a per core basis in the general CPU init. This touches all Sandybridge and Ivybridge configs. Change-Id: I015352d0f8e2ebe55ac0a5e9c5bbff83bd2ff86b Signed-off-by: Marc Jones <[email protected]> --- src/cpu/intel/model_206ax/finalize.c | 1 - src/cpu/intel/model_206ax/model_206ax_init.c | 26 ++++++++++++++------------ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index ca7048d..4ed5d1e 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -43,7 +43,6 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { - msr_set_bit(IA32_FEATURE_CONTROL, 0); msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 58593c8..f34c589 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -122,30 +122,32 @@ static void enable_vmx(void) msr_t msr; int enable = CONFIG_ENABLE_VMX; + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + msr = rdmsr(IA32_FEATURE_CONTROL); if (msr.lo & (1 << 0)) { - printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n"); + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); /* VMX locked. If we set it again we get an illegal * instruction */ return; } - regs = cpuid(1); + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); - if (regs.ecx & CPUID_VMX) { - if (enable) - msr.lo |= (1 << 2); - else - msr.lo &= ~(1 << 2); - if (regs.ecx & CPUID_SMX) { - if (enable) + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) msr.lo |= (1 << 1); - else - msr.lo &= ~(1 << 1); - } } wrmsr(IA32_FEATURE_CONTROL, msr); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
