Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1745
-gerrit commit d062b953392c307bf5e35b5751362f45afbbcf25 Author: Duncan Laurie <[email protected]> Date: Sun Sep 9 20:12:32 2012 -0700 SPI: re-init SMM SPI driver after lockdown If the driver is initialized before the lockdown then it will fail to work after the lockdown bit is set. Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a Signed-off-by: Duncan Laurie <[email protected]> --- src/southbridge/intel/bd82x6x/finalize.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 7bd9f3f..4a4f021 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -23,6 +23,7 @@ #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" +#include "spi.h" void intel_pch_finalize_smm(void) { @@ -35,6 +36,11 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); +#if CONFIG_SPI_FLASH_SMM + /* Re-init SPI driver to handle locked BAR */ + spi_init(); +#endif + /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
