Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1750
-gerrit commit c0cea87452780bc4982fa58c6bec0b3bc547c2d0 Author: Stefan Reinauer <[email protected]> Date: Wed Sep 19 10:32:25 2012 -0700 Add IGD Opregion variables to NVS In order to support Intel's IGD Opregion standard, we need an additional set of flags shared between firmware, ACPI, SMM, and the graphics driver. Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e Signed-off-by: Stefan Reinauer <[email protected]> --- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 20 ++++++-- src/southbridge/intel/bd82x6x/nvs.h | 58 +++++++++++++++--------- 2 files changed, 53 insertions(+), 25 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 7aeb32b..2fe092d 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 The Chromium OS Authors * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -150,7 +151,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) I509, 8, // 0xc1 - IGD 0509 modified settings I609, 8, // 0xc2 - IGD 0609 modified settings I709, 8, // 0xc3 - IGD 0709 modified settings - IDMM, 8, // 0xc4 - IGD DVMT Mode + IDMM, 8, // 0xc4 - IGD Power conservation feature IDMS, 8, // 0xc5 - IGD DVMT memory size IF1E, 8, // 0xc6 - IGD function 1 enable HVCO, 8, // 0xc7 - IGD HPLL VCO @@ -163,10 +164,23 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NXD7, 32, // 0xe0 - IGD _DGS next DID7 NXD8, 32, // 0xe4 - IGD _DGS next DID8 + ISCI, 8, // 0xe8 - IGD SMI/SCI mode (0: SCI) + PAVP, 8, // 0xe9 - IGD PAVP data + Offset (0xeb), + OSCC, 8, // 0xeb - PCIe OSC control + NPCE, 8, // 0xec - native pcie support + PLFL, 8, // 0xed - platform flavor + BREV, 8, // 0xee - board revision + DPBM, 8, // 0xef - digital port b mode + DPCM, 8, // 0xf0 - digital port c mode + DPDM, 8, // 0xf1 - digital port d mode + ALFP, 8, // 0xf2 - active lfp + IMON, 8, // 0xf3 - current graphics turbo imon value + MMIO, 8, // 0xf4 - 64bit mmio support + /* ChromeOS specific */ - Offset (0xf0), + Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> - // 0xe8a - end } /* Set flag to enable USB charging in S3 */ diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 2d94a64..3fa0093 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -95,10 +95,10 @@ typedef struct { u8 llow; u8 lhih; u8 rsvd7[0x6]; - /* EMA */ + /* Extended Mobile Access */ u8 emae; /* 0x78 - EMA enable */ - u16 emap; - u16 emal; + u16 emap; /* 0x79 - EMA pointer */ + u16 emal; /* 0x7a - EMA Length */ u8 rsvd8[0x5]; /* MEF */ u8 mefe; /* 0x82 - MEF enable */ @@ -116,25 +116,39 @@ typedef struct { u8 rsvd11[7]; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ - u8 ibtt; - u8 ipat; - u8 itvf; - u8 itvm; - u8 ipsc; - u8 iblc; - u8 ibia; - u8 issc; - u8 i409; - u8 i509; - u8 i609; - u8 i709; - u8 idmm; - u8 idms; - u8 if1e; - u8 hvco; - u32 nxd[8]; - u8 rsvd12[8]; - /* ChromeOS specific (starts at 0xf0)*/ + u8 ibtt; /* 0xb8 - IGD boot type */ + u8 ipat; /* 0xb9 - IGD panel type */ + u8 itvf; /* 0xba - IGD TV format */ + u8 itvm; /* 0xbb - IGD TV minor format */ + u8 ipsc; /* 0xbc - IGD Panel Scaling */ + u8 iblc; /* 0xbd - IGD BLC configuration */ + u8 ibia; /* 0xbe - IGD BIA configuration */ + u8 issc; /* 0xbf - IGD SSC configuration */ + u8 i409; /* 0xc0 - IGD 0409 modified settings */ + u8 i509; /* 0xc1 - IGD 0509 modified settings */ + u8 i609; /* 0xc2 - IGD 0609 modified settings */ + u8 i709; /* 0xc3 - IGD 0709 modified settings */ + u8 idmm; /* 0xc4 - IGD Power Conservation */ + u8 idms; /* 0xc5 - IGD DVMT memory size */ + u8 if1e; /* 0xc6 - IGD Function 1 Enable */ + u8 hvco; /* 0xc7 - IGD HPLL VCO */ + u32 nxd[8]; /* 0xc8 - IGD next state DIDx for _DGS */ + u8 isci; /* 0xe8 - IGD SMI/SCI mode (0: SCI) */ + u8 pavp; /* 0xe9 - IGD PAVP data */ + u8 rsvd12; /* 0xea - rsvd */ + u8 oscc; /* 0xeb - PCIe OSC control */ + u8 npce; /* 0xec - native pcie support */ + u8 plfl; /* 0xed - platform flavor */ + u8 brev; /* 0xee - board revision */ + u8 dpbm; /* 0xef - digital port b mode */ + u8 dpcm; /* 0xf0 - digital port c mode */ + u8 dpdm; /* 0xf1 - digital port c mode */ + u8 alfp; /* 0xf2 - active lfp */ + u8 imon; /* 0xf3 - current graphics turbo imon value */ + u8 mmio; /* 0xf4 - 64bit mmio support */ + u8 rsvd13[11]; /* 0xf5 - rsvd */ + + /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos; } __attribute__((packed)) global_nvs_t; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
