Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1773
-gerrit commit c4e5926a394ebf1c75a9503fe6baa678160324f8 Author: Duncan Laurie <[email protected]> Date: Mon Oct 8 15:26:54 2012 -0700 SPI: Configure Software Sequence SPI Freq to match descriptor Right now the SPI bus is getting set to 20mhz for transactions initiated with the software sequence interface. In order to be able to do reasonable fastread/write/erase we can bump this up to a higher value at boot before it gets locked at 20mhz. To do this read out the speed set in the SPI descriptor for hardware sequencing and apply it to software sequencing. Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4 Signed-off-by: Duncan Laurie <[email protected]> --- src/southbridge/intel/bd82x6x/bootblock.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0191bbf..7d0db7f 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -65,6 +65,26 @@ static void enable_port80_on_lpc(void) #endif } +static void set_spi_speed(void) +{ + u32 fdod; + u8 ssfc; + + /* Observe SPI Descriptor Component Section 0 */ + RCBA32(0x38b0) = 0x1000; + + /* Extract the Write/Erase SPI Frequency from descriptor */ + fdod = RCBA32(0x38b4); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + ssfc = RCBA8(0x3893); + ssfc &= ~7; + ssfc |= fdod; + RCBA8(0x3893) = ssfc; +} + static void bootblock_southbridge_init(void) { #if CONFIG_COLLECT_TIMESTAMPS @@ -72,6 +92,7 @@ static void bootblock_southbridge_init(void) #endif enable_spi_prefetch(); enable_port80_on_lpc(); + set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
