Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1831
-gerrit commit cdc32c8d02cc047582217e63c03e36d0be7c5998 Author: Kyösti Mälkki <[email protected]> Date: Tue Nov 13 23:28:31 2012 +0200 Fix HP DL165 bootblock The call to shc4307_init() was previously hooked as southbridge bootblock init. As a quick fix, hook this as a bootblock mainboard init. The real bootblock_southbridge_init is now also enabled, as it seems to be nothing but enable for top 4 MB flash decode. Change-Id: I02c6fe89ae9ad4a7403f024fac875ebd88a8e142 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/hp/dl165_g6_fam10/bootblock.c | 10 +++++++++- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index cdff24f..547cc21 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_BUS_CONFIG select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select HAS_MAINBOARD_BOOTBLOCK select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO @@ -90,10 +91,6 @@ config HEAP_SIZE hex default 0xc0000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "mainboard/hp/dl165_g6_fam10/bootblock.c" - config MMCONF_SUPPORT_DEFAULT bool default y diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c index 2c56c4c..9db67f7 100644 --- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c +++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c @@ -18,6 +18,9 @@ static inline void shc4307_exit_ext_func_mode(device_t dev) #define DBG_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0x3) #define REGS_DEV PNP_DEV(SCH4307_CONFIG_PORT, 0xa) +/* FIXME: This appears to be a super-io initialisation, + * placed in the mainboard directory. + */ void shc4307_init(void) { shc4307_enter_ext_func_mode(CMOS_DEV); @@ -43,6 +46,11 @@ void shc4307_init(void) shc4307_exit_ext_func_mode(CMOS_DEV); } -static void bootblock_southbridge_init(void) { +static unsigned long init_mainboard(int bsp_cpu) +{ + if (!bsp_cpu) return 0; + bootblock_northbridge_init(); + bootblock_southbridge_init(); shc4307_init(); + return 0; } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
