Zheng Bao ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1920
-gerrit commit 5454b20194a1769bfaa2cecd166fb6cdf317e0cf Author: Zheng Bao <[email protected]> Date: Tue Nov 27 17:00:17 2012 +0800 AMD S3: Leverage the public SPI routine Remove the old, unflexible code for storing data in SPI flash. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <[email protected]> Signed-off-by: zbao <[email protected]> --- src/cpu/amd/agesa/s3_resume.c | 88 ++++++------ src/southbridge/amd/Kconfig | 4 + src/southbridge/amd/agesa/hudson/spi.c | 254 ++++++++++----------------------- src/southbridge/amd/agesa/hudson/spi.h | 43 ------ 4 files changed, 116 insertions(+), 273 deletions(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 0348a9f..6302c3d 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -41,7 +41,8 @@ #include "agesawrapper.h" #ifndef __PRE_RAM__ -#include "spi.h" +#include <spi.h> +#include <spi_flash.h> #endif void restore_mtrr(void) @@ -151,14 +152,18 @@ void move_stack_high_mem(void) void OemAgesaSaveMtrr(void) { #ifndef __PRE_RAM__ - u32 spi_address; msr_t msr_data; - device_t dev; u32 nvram_pos = S3_DATA_MTRR_POS; u32 i; + struct spi_flash *flash; - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + return; + } /* Enable access to AMD RdDram and WrDram extension bits */ msr_data = rdmsr(SYS_CFG); @@ -167,28 +172,29 @@ void OemAgesaSaveMtrr(void) /* Fixed MTRRs */ msr_data = rdmsr(0x250); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x258); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; msr_data = rdmsr(0x259); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; for (i = 0x268; i < 0x270; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } @@ -200,35 +206,33 @@ void OemAgesaSaveMtrr(void) /* Variable MTRRs */ for (i = 0x200; i < 0x210; i++) { msr_data = rdmsr(i); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; } /* SYS_CFG */ msr_data = rdmsr(0xC0010010); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM */ msr_data = rdmsr(0xC001001A); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; /* TOM2 */ msr_data = rdmsr(0xC001001D); - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.lo); + flash->write(flash, nvram_pos, 4, &msr_data.lo); nvram_pos += 4; - dword_noneAAI_program((u8 *) spi_address, nvram_pos, msr_data.hi); + flash->write(flash, nvram_pos, 4, &msr_data.hi); nvram_pos += 4; - write_spi_status((u8 *)spi_address, 0x3c); - spi_write_disable((u8 *) spi_address); #endif } @@ -251,9 +255,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) { u32 pos = S3_DATA_VOLATILE_POS; - u32 spi_address, data; + u32 data; u32 nvram_pos; - device_t dev; + struct spi_flash *flash; if (S3DataType == S3DataTypeNonVolatile) { pos = S3_DATA_NONVOLATILE_POS; @@ -261,39 +265,27 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) pos = S3_DATA_VOLATILE_POS; } - dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); - spi_address = pci_read_config32(dev, 0xA0) & ~0x1F; + spi_init(); + flash = spi_flash_probe(0, 0, 0, 0); + if (!flash) { + printk(BIOS_DEBUG, "Could not find SPI device\n"); + /* Dont make flow stop. */ + return AGESA_SUCCESS; + } - /* printk(BIOS_DEBUG, "spi_address=%x\n", spi_address); */ - read_spi_id((u8 *) spi_address); - write_spi_status((u8 *)spi_address, 0); if (S3DataType == S3DataTypeNonVolatile) { - sector_erase_spi((u8 *) spi_address, S3_DATA_NONVOLATILE_POS); + flash->erase(flash, S3_DATA_NONVOLATILE_POS, 0x1000); } else { - sector_erase_spi((u8 *) spi_address, S3_DATA_VOLATILE_POS); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x1000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x2000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x3000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x4000); - sector_erase_spi((u8 *) spi_address, - S3_DATA_VOLATILE_POS + 0x5000); + flash->erase(flash, S3_DATA_VOLATILE_POS, 0x6000); } nvram_pos = 0; - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos, DataSize); + flash->write(flash, nvram_pos + pos, sizeof(DataSize), &DataSize); for (nvram_pos = 0; nvram_pos < DataSize; nvram_pos += 4) { data = *(u32 *) (Data + nvram_pos); - dword_noneAAI_program((u8 *) spi_address, nvram_pos + pos + 4, - *(u32 *) (Data + nvram_pos)); + flash->write(flash, nvram_pos + pos + 4, sizeof(u32), (u32 *)(Data + nvram_pos)); } - /* write_spi_status((u8 *)spi_address, 0x3c); */ - - /* spi_write_disable((u8 *) spi_address); */ return AGESA_SUCCESS; } diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 867afca..20d5573 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,3 +14,7 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig + +config SPI_FLASH + bool + default y if HAVE_ACPI_RESUME && CPU_AMD_AGESA diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index ad8b6d4..b4f6775 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,218 +1,108 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <console/console.h> +#include <stdint.h> +#include <stdlib.h> #include <arch/io.h> + +#include <spi.h> +#include <spi_flash.h> + #include <device/device.h> -#include "spi.h" +#include <device/pci.h> +#include <device/pci_ops.h> -void execute_command(volatile u8 * spi_address) -{ - *(spi_address + 2) |= 1; -} +static u32 spibar; -void wait4command_complete(volatile u8 * spi_address) +static void reset_internal_fifo_pointer(void) { -// while (*(spi_address + 2) & 1) - while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80)) - printk(BIOS_DEBUG, "wait4CommandComplete\n"); + do { + write8(spibar + 2, read8(spibar + 2) | 0x10); + } while (read8(spibar + 0xD) & 0x7); } -void reset_internal_fifo_pointer(volatile u8 * spi_address) +static void execute_command(void) { - u8 val; + write8(spibar + 2, read8(spibar + 2) | 1); - do { - *(spi_address + 2) |= 0x10; - val = *(spi_address + 0xd); - } while (val & 0x7); + while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); } -u8 read_spi_status(volatile u8 * spi_address) +void spi_init() { - u8 val; - *spi_address = 0x05; - *(spi_address + 1) = 0x21; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0x0; /* dummy */ - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - val = *(spi_address + 0xC); - return val; -} + device_t dev; -void wait4flashpart_ready(volatile u8 * spi_address) -{ - while (read_spi_status(spi_address) & 1) ; + dev = dev_find_slot(0, PCI_DEVFN(0x14, 3)); + spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } -void write_spi_status(volatile u8 * spi_address, u8 status) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { - *spi_address = 0x50; /* EWSR */ - *(spi_address + 1) = 0; /* RxByte=TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); - - *spi_address = 0x01; /* WRSR */ - *(spi_address + 1) = 0x01; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = status; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); - - read_spi_status(spi_address); -} + /* First byte is cmd which can not being sent through FIFO. */ + u8 cmd = *(u8 *)dout++; + u8 readoffby1; + u8 readwrite; + u8 bytesout, bytesin; + u8 count; -void read_spi_id(volatile u8 * spi_address) -{ - u8 mid = 0, did = 0; - *spi_address = 0x90; - *(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */ - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - *(spi_address + 0xC) = 0; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - reset_internal_fifo_pointer(spi_address); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - mid = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); - - mid = *(spi_address + 0xC); - did = *(spi_address + 0xC); - printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did); -} + bitsout -= 8; + bytesout = bitsout / 8; + bytesin = bitsin / 8; -void spi_write_enable(volatile u8 * spi_address) -{ - *spi_address = 0x06; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); -} + readoffby1 = bytesout ? 0 : 1; + + readwrite = (bytesin + readoffby1) << 4 | bytesout; + write8(spibar+1, readwrite); + write8(spibar + 0, cmd); + + reset_internal_fifo_pointer(); -void spi_write_disable(volatile u8 * spi_address) + for (count = 0; count < bytesout; count++, dout++) { + write8(spibar + 0x0C, *(u8 *)dout); + } + + reset_internal_fifo_pointer(); + + execute_command(); + + reset_internal_fifo_pointer(); + + /* Skip the bytes we sent. */ + for (count = 0; count < bytesout; count++) { + cmd = read8(spibar + 0x0C); + } + reset_internal_fifo_pointer(); + for (count = 0; count < bytesin; count++, din++) { + *(u8 *)din = read8(spibar + 0x0C); + } + + return 0; +} +int spi_claim_bus(struct spi_slave *slave) { - *spi_address = 0x04; /* Write Enable */ - *(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */ - execute_command(spi_address); - wait4command_complete(spi_address); + return 0; } -void sector_erase_spi(volatile u8 * spi_address, u32 address) +void spi_release_bus(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x20; - *(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */ - - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void chip_erase_spi(volatile u8 * spi_address) +void spi_cs_activate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0xC7; - *(spi_address + 1) = 0x00; - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void byte_program(volatile u8 * spi_address, u32 address, u32 data) +void spi_cs_deactivate(struct spi_slave *slave) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); } -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { - u8 i; - /* - * printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data); - */ - for (i = 0; i < 4; i++) { - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 4; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - data >>= 8; - address++; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); + struct spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + return NULL; } -} -void dword_program(volatile u8 * spi_address, u32 address, u32 data) -{ - spi_write_enable(spi_address); - *spi_address = 0x02; - *(spi_address + 1) = 0x0 << 4 | 7; - reset_internal_fifo_pointer(spi_address); - *(spi_address + 0xC) = (address >> 16) & 0xFF; - *(spi_address + 0xC) = (address >> 8) & 0xFF; - *(spi_address + 0xC) = (address >> 0) & 0xFF; - *(spi_address + 0xC) = data & 0xFF; - *(spi_address + 0xC) = (data >> 8) & 0xFF; - *(spi_address + 0xC) = (data >> 16) & 0xFF; - *(spi_address + 0xC) = (data >> 24) & 0xFF; - reset_internal_fifo_pointer(spi_address); - execute_command(spi_address); - wait4command_complete(spi_address); - wait4flashpart_ready(spi_address); -} + memset(slave, 0, sizeof(*slave)); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data) -{ - spi_write_enable(spi_address); - *address = data; - wait4flashpart_ready(spi_address); + return slave; } diff --git a/src/southbridge/amd/agesa/hudson/spi.h b/src/southbridge/amd/agesa/hudson/spi.h deleted file mode 100644 index 657ce4e..0000000 --- a/src/southbridge/amd/agesa/hudson/spi.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - ***************************************************************************** - * - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * *************************************************************************** - * - */ - -#ifndef _HUDSON_CIMX_SPI_H_ -#define _HUDSON_CIMX_SPI_H_ - -void execute_command(volatile u8 * spi_address); -void wait4command_complete(volatile u8 * spi_address); -void reset_internal_fifo_pointer(volatile u8 * spi_address); -u8 read_spi_status(volatile u8 * spi_address); -void wait4flashpart_ready(volatile u8 * spi_address); -void write_spi_status(volatile u8 * spi_address, u8 status); -void read_spi_id(volatile u8 * spi_address); -void spi_write_enable(volatile u8 * spi_address); -void spi_write_disable(volatile u8 * spi_address); -void sector_erase_spi(volatile u8 * spi_address, u32 address); -void chip_erase_spi(volatile u8 * spi_address); -void byte_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data); -void dword_program(volatile u8 * spi_address, u32 address, u32 data); -void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data); - -#endif -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
