Marc Jones ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1965
-gerrit commit cb98e70f96b43d6d1c4eacfb18af17ee0c26ad4d Author: Marc Jones <[email protected]> Date: Mon Dec 3 22:16:29 2012 -0700 FIX a few SPI device debug prints to use CONFIG_DEBUG_SPI_FLASH Fix a few debug printks that were not using CONFIG_DEBUG_SPI_FLASH. With debug SPEW enabled, the boot would increase, to an unacceptable, 30 seconds. Change-Id: I99fc3d5f847fdf4bb98e2a0342ea418ab7d5fc54 Signed-off-by: Marc Jones <[email protected]> --- src/drivers/spi/spi_flash.c | 3 ++- src/drivers/spi/sst.c | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 7116cbf..75a5c21 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -162,9 +162,10 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u8 erase_cmd, spi_flash_addr(offset, cmd); offset += erase_size; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], cmd[2], cmd[3], offset); - +#endif ret = spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0); if (ret) goto out; diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index ebeb441..4ba9ca6 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -130,8 +130,10 @@ sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf) offset, }; +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(flash->spi, CMD_SST_RDSR), buf, cmd[0], offset); +#endif ret = sst_enable_writing(flash); if (ret) @@ -177,9 +179,11 @@ sst_write(struct spi_flash *flash, u32 offset, size_t len, const void *buf) cmd[3] = offset; for (; actual < len - 1; actual += 2) { +#if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n", spi_w8r8(flash->spi, CMD_SST_RDSR), buf + actual, cmd[0], offset); +#endif ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, buf + actual, 2); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
