David Hendricks ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2130
-gerrit commit 08cf2c5d57576183c04d69882f23464c082bcda9 Author: David Hendricks <[email protected]> Date: Thu Jan 10 11:44:58 2013 -0800 armv7: replace magic constant for romstage location This replaces 0x02023400 with an SoC-specific Kconfig variable. Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551 Signed-off-by: David Hendricks <[email protected]> --- src/arch/armv7/romstage.ld | 3 +-- src/mainboard/google/snow/Kconfig | 4 ++++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index d2b69d7..5d045b5 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -39,8 +39,7 @@ ENTRY(_start) SECTIONS { - /* FIXME: replace this with CPU-specific Kconfig variable */ - . = 0x02023400; /* Exynos5 */ + . = CONFIG_ROMSTAGE_BASE; .romtext . : { _rom = .; diff --git a/src/mainboard/google/snow/Kconfig b/src/mainboard/google/snow/Kconfig index 4a7fced..21cdfa5 100644 --- a/src/mainboard/google/snow/Kconfig +++ b/src/mainboard/google/snow/Kconfig @@ -63,6 +63,10 @@ config SPL_TEXT_BASE help Location of SPL. Default location is within iRAM region. +config ROMSTAGE_BASE + hex + default SPL_TEXT_BASE + # FIXME: increased "SPL" size to get around build issues #config SPL_MAX_SIZE # hex "SPL executable max size" -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
