Dear coreboot Gerrit folks,
I did `git checkout` of Konstantin’s patch [1] and improved the commit
message. Wanting to push it, I get the following error.
$ git push
Counting objects: 49, done.
Delta compression using up to 2 threads.
Compressing objects: 100% (30/30), done.
Writing objects: 100% (30/30), 12.81 KiB, done.
Total 30 (delta 21), reused 0 (delta 0)
remote: Resolving deltas: 100% (21/21)
remote: Processing changes: refs: 1, done
To ssh://[email protected]:29418/coreboot
! [remote rejected] HEAD -> refs/for/master (not Signed-off-by
author/committer/uploader)
error: failed to push some refs to
'ssh://[email protected]:29418/coreboot'
$ git show
commit 76852159e877b6f88a9da8378691ebae11c88e3d
Author: Konstantin Aladyshev <[email protected]>
Date: Fri Jan 25 19:20:51 2013 +0400
Supermicro H8QGI: Substract 1 from MMCONF range limit
MMCONF space is defined by two config parameters:
MMCONF_BASE_ADDRESS (0xF800 0000)
MMCONF_BUS_NUMBER (64)
coreboot allocates 1 MB per bus, so MMCONF limit should be:
0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF
Current code does not have (-1) component, this makes MMCONF limit
equal 0xFC00 FFFF. Add (-1) to correct this issue.
No functionality change has been experienced. The five times
slower RAM speed compared to the proprietary vendor BIOS still
remains.
Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
Signed-off-by: Konstantin Aladyshev <[email protected]>
Signed-off-by: Aladyshev Konstantin <[email protected]>
Signed-off-by: Paul Menzel <[email protected]>
diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c
b/src/mainboard/supermicro/h8qgi/agesawrapper.c
index 9720bed..517e136 100644
--- a/src/mainboard/supermicro/h8qgi/agesawrapper.c
+++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c
@@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
* coreboot not implemente the range by range setting
yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB +
node, FUNC_1, 0xBC);
- PciData = CONFIG_MMCONF_BASE_ADDRESS +
(CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
+ PciData = CONFIG_MMCONF_BASE_ADDRESS +
(CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;
Adding my Signed-off-by line did not help neither adding Konstantin’s
one with his first and family name reversed.
I guess it might be related to the switch of first and last name I asked
him to do.
Thanks,
Paul
[1] http://review.coreboot.org/#/c/2193/
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