Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2337
-gerrit commit ff95c8ab670f793d1e00490d8f1dfeefc6166184 Author: Patrick Georgi <[email protected]> Date: Sat Feb 9 15:35:30 2013 +0100 speedstep: Deduplicate some MSR identifiers In particular: MSR_PMG_CST_CONFIG_CONTROL MSR_PMG_IO_BASE_ADDR MSR_PMG_IO_CAPTURE_ADDR Change-Id: Ief2697312f0edf8c45f7d3550a7bedaff1b69dc6 Signed-off-by: Patrick Georgi <[email protected]> --- src/cpu/intel/model_1067x/model_1067x_init.c | 15 ++++++--------- src/cpu/intel/model_106cx/model_106cx_init.c | 12 ++++-------- src/cpu/intel/model_206ax/finalize.c | 1 + src/cpu/intel/model_206ax/model_206ax.h | 2 -- src/cpu/intel/model_6ex/model_6ex_init.c | 12 ++++-------- src/cpu/intel/model_6fx/model_6fx_init.c | 12 ++++-------- src/include/cpu/intel/speedstep.h | 3 +++ 7 files changed, 22 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 2b7839b..e81a6a7 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -98,9 +98,6 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_BBL_CR_CTL3 0x11e #define MSR_FSB_FREQ 0xcd @@ -123,7 +120,7 @@ static void configure_c_states(const int quad) const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) { @@ -140,17 +137,17 @@ static void configure_c_states(const int quad) msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set IO Capture Address */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | ((cst_range & 0xffff) << 16); - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); if (c5) { msr = rdmsr(MSR_BBL_CR_CTL3); @@ -188,10 +185,10 @@ static void configure_p_states(const char stepping, const char cores) wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 4bf2924..803875d 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -80,34 +80,30 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; // TODO Do we want PM1_BASE? Needs SMM? //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); msr.lo = ((PMB0_BASE + 4) & 0xffff); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 4ed5d1e..9e7c3fa 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -22,6 +22,7 @@ #include <stdlib.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/intel/speedstep.h> #include "model_206ax.h" static void msr_set_bit(unsigned reg, unsigned bit) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index a7ca04a..d440c70 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -48,8 +48,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 9dbb137..2e25553 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -77,16 +77,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset. msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk @@ -96,17 +92,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* set C_LVL controls */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 3cdfdc4..d7c8d51 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -91,16 +91,12 @@ static void enable_vmx(void) wrmsr(IA32_FEATURE_CONTROL, msr); } -#define PMG_CST_CONFIG_CONTROL 0xe2 -#define PMG_IO_BASE_ADDR 0xe3 -#define PMG_IO_CAPTURE_ADDR 0xe4 - #define HIGHEST_CLEVEL 3 static void configure_c_states(void) { msr_t msr; - msr = rdmsr(PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep @@ -112,17 +108,17 @@ static void configure_c_states(void) msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); - wrmsr(PMG_IO_BASE_ADDR, msr); + wrmsr(MSR_PMG_IO_BASE_ADDR, msr); /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted - wrmsr(PMG_IO_CAPTURE_ADDR, msr); + wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } #define IA32_MISC_ENABLE 0x1a0 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index b5d1d68..86778b1 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -46,6 +46,9 @@ #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 #define MSR_FSB_CLOCK_VCC 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PMG_IO_BASE_ADDR 0xe3 +#define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
