David Hendricks ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2361
-gerrit commit 8f5fa1a3234d79904e79da78fd1ef3e3892156d1 Author: David Hendricks <[email protected]> Date: Mon Feb 11 16:05:33 2013 -0800 exynos5250: add memory resources (dirty hack) ** do not submit ** this is just a dirty hack to get the resource allocator to add memory. Change-Id: Ifb264ff159d45ad2f0fd8656abd6cb47fc14c7ac Signed-off-by: Stefan Reinauer <[email protected]> Signed-off-by: David Hendricks <[email protected]> --- src/arch/armv7/boot/coreboot_table.c | 4 -- src/cpu/samsung/exynos5250/Makefile.inc | 1 + src/cpu/samsung/exynos5250/cpu.c | 66 +++++++++++++++++++++++++++++++++ src/device/device.c | 1 + src/mainboard/google/snow/devicetree.cb | 6 +++ src/mainboard/google/snow/mainboard.c | 21 +++++++++++ src/mainboard/google/snow/ramstage.c | 36 ++++++++++++++++++ 7 files changed, 131 insertions(+), 4 deletions(-) diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index ed105a4..76fc8fb 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -559,13 +559,11 @@ struct lb_memory *get_lb_mem(void) return mem_ranges; } -#if 0 static void build_lb_mem_range(void *gp, struct device *dev, struct resource *res) { struct lb_memory *mem = gp; new_lb_memory_range(mem, LB_MEM_RAM, res->base, res->size); } -#endif static struct lb_memory *build_lb_mem(struct lb_header *head) { @@ -576,12 +574,10 @@ static struct lb_memory *build_lb_mem(struct lb_header *head) mem_ranges = mem; /* FIXME: implement this */ -#if 0 /* Build the raw table of memory */ search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, build_lb_mem_range, mem); -#endif /* FIXME: things die in cleanup_memory_ranges(), skip for now */ // lb_cleanup_memory_ranges(mem); return mem; diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 0a58c0c..5244692 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -27,6 +27,7 @@ ramstage-y += pinmux.c ramstage-y += power.c ramstage-y += soc.c ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-y += cpu.c #ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c #ramstage-$(CONFIG_SATA_AHCI) += sata.c diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c new file mode 100644 index 0000000..745bf1a --- /dev/null +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -0,0 +1,66 @@ +#include <console/console.h> +#include <device/device.h> + +static void my_pci_domain_read_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: ENTERED!!\n", __func__); + ram_resource(dev, 0, + (CONFIG_SYS_SDRAM_BASE >> 10) + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_ROMSIZE_KB +/* - (CONFIG_COREBOOT_TABLES_SIZE >> 10) */); +} + +static void my_pci_domain_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: ENTERED!!\n", __func__); + assign_resources(dev->link_list); +} + +static unsigned int my_pci_domain_scan_bus(device_t dev, unsigned int max) +{ + //max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); + return max; +} + + +static struct device_operations pci_domain_ops = { + .read_resources = my_pci_domain_read_resources, + .set_resources = my_pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = my_pci_domain_scan_bus, +}; + +static void cpu_bus_init(device_t dev) +{ + printk(BIOS_DEBUG,"INITIALIZE CPUS!\n"); + //initialize_cpus(dev->link_list); +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + printk (BIOS_DEBUG, "OUR CPU CHIP OPS!!\n"); + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations cpu_samsung_exynos5250_ops = { + CHIP_NAME("CPU Samsung Exynos 5250") + .enable_dev = enable_dev, +}; diff --git a/src/device/device.c b/src/device/device.c index 07bbc7a..7c8905b 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -812,6 +812,7 @@ void assign_resources(struct bus *bus) dev_path(bus->dev), bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { + printk(BIOS_DEBUG, "curdev=%s\n", dev_path(curdev)); if (!curdev->enabled || !curdev->resource_list) continue; diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index f88835e..5f5de32 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -19,8 +19,14 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 + +device lapic_cluster 0 on +end + +device pci_domain 0 on chip drivers/generic/generic # I2C0 controller device i2c 6 on end # ? device i2c 9 on end # ? end end +end diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index efe6672..79d5715 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -69,6 +69,27 @@ int board_get_config(void) } #if 0 +static void mainboard_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + /* Report the memory regions */ + ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE); + + assign_resources(dev->link_list); +} + +static struct device_operations mainboard_device_ops = { + .set_resources = mainboard_set_resources, +} + +static void mainboard_enable(device_t dev) +{ + dev->ops = &mainboard_device_ops; +} + struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM ChromeBook", .enable_dev = mainboard_enable, diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index a3e9236..e144388 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,6 +18,7 @@ */ #include <console/console.h> +#include <device/device.h> #if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> @@ -39,3 +40,38 @@ void main(void) hardwaremain(0); } + +#if 0 +static void mainboard_read_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + /* Report the memory regions */ + ram_resource(dev, 0, + CONFIG_SYS_SDRAM_BASE + (CONFIG_COREBOOT_ROMSIZE_KB), + ((CONFIG_DRAM_SIZE_MB << 10UL) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE); +} + +static void mainboard_set_resources(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + + assign_resources(dev->link_list); +} + +static struct device_operations mainboard_device_ops = { + .read_resources = mainboard_read_resources, + .set_resources = mainboard_set_resources, +}; +#endif + +static void mainboard_enable(device_t dev) +{ + printk(BIOS_DEBUG, "%s: entered\n", __func__); + //dev->ops = &mainboard_device_ops; +} + +struct chip_operations mainboard_ops = { + .name = "Samsung/Google ARM ChromeBook", + .enable_dev = mainboard_enable, +}; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
