David Hendricks ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2379
-gerrit commit 5696e9df858e0969d3ea0aa4aa8b3b3e9a43bbb5 Author: David Hendricks <[email protected]> Date: Tue Feb 12 15:37:12 2013 -0800 snow: Set up MMU after DRAM is working This was omitted earlier while we were debugging DRAM code (0a5bc7f). It was likely broken due to inconsistent units earlier on. Now that things are cleaned up and working, let's add it back in. Change-Id: I2f356355c98b2896e2371fa63b9c9f20ae76d634 Signed-off-by: David Hendricks <[email protected]> --- src/mainboard/google/snow/romstage.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 719337b..f6f858c 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -85,6 +85,8 @@ void main(void) printk(BIOS_INFO, "ddr3_init done\n"); + mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
