Jens Rottmann ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454
-gerrit commit 4b48791ecd0090cae99d0da6400f42f979da3c8c Author: Jens Rottmann <[email protected]> Date: Tue Feb 19 15:01:06 2013 +0100 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio The power up default for 14M_25M_48M_OSC is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz. We could switch back to 14 in the mainboard's romstage.c, but then the clock frequency would change twice. This patch skips the SB800 clock switch if the SIO is smscsuperio. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <[email protected]> --- src/southbridge/amd/cimx/sb800/bootblock.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..8e88f4b 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,13 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl to enable 14M_25M_48M_OSC clock output + // usually used for the Super-I/O reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz +#ifndef CONFIG_SUPERIO_SMSC_SMSCSUPERIO + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
