Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2544
-gerrit commit 57fbf0b3522d77f668741b6e65681aaadef7d97d Author: Kyösti Mälkki <[email protected]> Date: Tue Feb 26 23:05:00 2013 +0200 Rename i82801 enable_ioapic to general_cntl The writes to IOAPIC address space is moved outside this function. New name is the PCI config register touched. Change-Id: Id7e5e63a99cbc043669bce8495886fa687756149 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/southbridge/intel/i82801ax/lpc.c | 9 ++++----- src/southbridge/intel/i82801bx/lpc.c | 10 ++++------ src/southbridge/intel/i82801cx/lpc.c | 9 ++++----- src/southbridge/intel/i82801dx/lpc.c | 9 ++++----- 4 files changed, 16 insertions(+), 21 deletions(-) diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 1d296f4..8d4850d 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -91,7 +91,7 @@ static void i82801ax_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801ax_enable_ioapic(struct device *dev) +static void i82801ax_general_cntl(struct device *dev) { u32 reg32; @@ -101,9 +101,7 @@ static void i82801ax_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -222,8 +220,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801ax_enable_acpi(dev); + i82801ax_general_cntl(dev); /* IO APIC initialization. */ - i82801ax_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801ax_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0533afb..2b36390 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -92,7 +92,7 @@ static void i82801bx_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801bx_enable_ioapic(struct device *dev) +static void i82801bx_general_cntl(struct device *dev) { u32 reg32; @@ -102,9 +102,7 @@ static void i82801bx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -239,9 +237,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801bx_enable_acpi(dev); - + i82801bx_general_cntl(dev); /* IO APIC initialization. */ - i82801bx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801bx_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 79998bc..c6e296e 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -29,7 +29,7 @@ * * @param dev PCI device with I/O APIC control registers */ -static void i82801cx_enable_ioapic(struct device *dev) +static void i82801cx_general_cntl(struct device *dev) { u32 reg32; @@ -39,9 +39,7 @@ static void i82801cx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } // This is how interrupts are received from the Super I/O chip @@ -150,8 +148,9 @@ static void lpc_init(struct device *dev) int pwr_on=-1; int nmi_option; + i82801cx_general_cntl(dev); /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801cx_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 0644569..83f6ed9 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -55,7 +55,7 @@ static void i82801dx_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801dx_enable_ioapic(struct device *dev) +static void i82801dx_general_cntl(struct device *dev) { u32 reg32; @@ -65,9 +65,7 @@ static void i82801dx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -269,8 +267,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801dx_enable_acpi(dev); + i82801dx_general_cntl(dev); /* IO APIC initialization. */ - i82801dx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801dx_enable_serial_irqs(dev); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
