Ronald G. Minnich ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2585
-gerrit commit 190b6f6f72c823a93fbf836b16a023434f955743 Author: Ronald G. Minnich <[email protected]> Date: Mon Mar 4 16:39:35 2013 -0800 google/snow: enable MMC0 Most of the code to enable MMC0 was here, we just needed to set the pinmux. On snow, it's 8 bits. Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9 Signed-off-by: Ronald G. Minnich <[email protected]> --- src/mainboard/google/snow/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c index 7e1cd57..46a4e8f 100644 --- a/src/mainboard/google/snow/romstage.c +++ b/src/mainboard/google/snow/romstage.c @@ -63,7 +63,7 @@ static void initialize_s5p_mshc(void) { gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X); /* TODO(hungte) Change 0 to PINMUX_FLAG_8BIT_MODE when the s5p_mshc * driver is ready. */ - exynos_pinmux_config(PERIPH_ID_SDMMC0, 0); + exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE); /* MMC2: Removable, 4 bit mode, no GPIO. */ clock_set_mshci(PERIPH_ID_SDMMC2); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
