Ronald G. Minnich ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2587
-gerrit commit 840574bcf408d9b66904600c99af280fb4b3b9df Author: Ronald G. Minnich <[email protected]> Date: Wed Mar 6 08:50:50 2013 -0800 Google/Snow: enable sound hardware clocks Set up the clocks used for sound and turn on the sound clock. Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8 Signed-off-by: Gabe Black <[email protected]> Signed-off-by: Ronald G. Minnich <[email protected]> --- src/mainboard/google/snow/ramstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index 5970357..9f259ef 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -19,6 +19,8 @@ #include <console/console.h> #include <cbmem.h> +#include <cpu/samsung/exynos5250/clk.h> +#include <cpu/samsung/exynos5250/power.h> void hardwaremain(int boot_complete); void main(void) @@ -32,5 +34,14 @@ void main(void) ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_TABLES_SIZE; + const unsigned epll_hz = 192000000; + const unsigned sample_rate = 48000; + const unsigned lr_frame_size = 256; + clock_epll_set_rate(epll_hz); + clock_select_i2s_clk_source(); + clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size); + + power_enable_xclkout(); + hardwaremain(0); } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
