Mike Loptien ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2592
-gerrit commit 969e55b868fd2fcb5e02cde02447a894f158245b Author: Mike Loptien <[email protected]> Date: Tue Mar 5 14:21:28 2013 -0700 Persimmon DSDT: Add secondary bus range to PCI0 Adding the 'WordBusNumber' macro to the PCI0 CRES ResourceTemplate in the Persimmon DSDT. This sets up the bus number for the PCI0 device and the secondary bus number for the CRS method. This change came in response to a 'dmesg' error which states: '[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS' By adding the 'WordBusNumber' macro, ACPI can set up a valid range for the PCIe downstream busses, thereby relieving the Linux kernel from "guessing" the valid range based off _BBN or assuming [0-0xFF]. The Linux kernel code that checks this bus range is in `drivers/acpi/pci_root.c`. This change will apply to other AMD mainboards and will be in a different commit. Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860 Signed-off-by: Mike Loptien <[email protected]> --- src/mainboard/amd/persimmon/dsdt.asl | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index 582ab7f..06e407d 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -1157,6 +1157,8 @@ DefinitionBlock ( Device(PCI0) { External (TOM1) External (TOM2) + Name (PSBB, 0x0000) /* Secondary bus base variable for PCI0 */ + Name (PSBL, 0x00FF) /* Secondary bus length variable for PCI0 */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1477,14 +1479,23 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + /* This sets the Bus number and Secondary Bus number for the PCI0 device */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x007F, /* range maximum */ + 0x0000, /* translation */ + 0x0080, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, /* address granularity */ - 0x0000, /* range minimum */ - 0x0CF7, /* range maximum */ - 0x0000, /* translation */ - 0x0CF8 /* length */ + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ ) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, @@ -1581,6 +1592,16 @@ DefinitionBlock ( Store(PBLN,EBML) } #endif + /* This sets up the secondary bus range for PCI0. */ + CreateWordField (CRES, ^PSB0._MIN, MIN0) + CreateWordField (CRES, ^PSB0._MAX, MAX0) + CreateWordField (CRES, ^PSB0._LEN, LEN0) + + Store (PSBB, MIN0) /* Put Secondary Bus Base value into MIN0 memory */ + Store (PSBL, LEN0) /* Put Secondary Bus Length value into LEN0 memory */ + Store (LEN0, Local0) /* Copy into Local0 for doing math */ + Add (MIN0, Decrement (Local0), MAX0) /* Add MIN0 to Local0 and put it into MAX0 memory */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L) /* -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
