Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2629
-gerrit commit e0582a01e7302c01e49d7eb02bd52dc4136d22d5 Author: Aaron Durbin <[email protected]> Date: Mon Nov 12 10:14:55 2012 -0600 haswell: use #defines for constants in udelay.c Change the hard coded values in udelay.c to use the #defines for MSRs and BCLK. Change-Id: I2bbeb0b478d2e3ca155e8f82006df86c29a4f018 Signed-off-by: Aaron Durbin <[email protected]> --- src/northbridge/intel/haswell/udelay.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/haswell/udelay.c b/src/northbridge/intel/haswell/udelay.c index 864e839..f5d541e 100644 --- a/src/northbridge/intel/haswell/udelay.c +++ b/src/northbridge/intel/haswell/udelay.c @@ -21,10 +21,7 @@ #include <stdint.h> #include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> - -/** - * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz - */ +#include "cpu/intel/haswell/haswell.h" /* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */ static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b) @@ -42,13 +39,13 @@ void udelay(u32 us) u32 dword; tsc_t tsc, tsc1, tscd; msr_t msr; - u32 fsb = 100, divisor; + u32 divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xce); + msr = rdmsr(MSR_PLATFORM_INFO); divisor = (msr.lo >> 8) & 0xff; - d = fsb * divisor; /* On Core/Core2 this is divided by 4 */ + d = HASWELL_BCLK * divisor; multiply_to_tsc(&tscd, us, d); tsc1 = rdtsc(); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
