Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2633
-gerrit commit 84486e92c53e4f34b863b4fbca91c6db4e02c3e3 Author: Aaron Durbin <[email protected]> Date: Fri Dec 7 09:50:40 2012 -0600 haswell: Remove logic to send dram init done to ME The reference code sends the dram init done command to the ME. Therefore, there is no need for coreboot to do this. Change-Id: I6837d6c50bbb7db991f9d21fc9cdba76252c1b7b Signed-off-by: Aaron Durbin <[email protected]> --- src/northbridge/intel/haswell/raminit.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 09c8fc4..0c68e60 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -216,13 +216,7 @@ void sdram_initialize(struct pei_data *pei_data) version >> 24 , (version >> 16) & 0xff, (version >> 8) & 0xff, version & 0xff); - /* Send ME init done for SandyBridge here. This is done - * inside the SystemAgent binary on IvyBridge. */ - if (BASE_REV_SNB == - (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) - intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); - else - intel_early_me_status(); + intel_early_me_status(); report_memory_config(); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
