Stefan Reinauer ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2680
-gerrit commit 3584a9b36e56bf2c3dcb6365c146c5fa1db141ee Author: Duncan Laurie <[email protected]> Date: Wed Dec 19 09:12:31 2012 -0800 haswell: more ULT/LP support and minor tweaks - Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <[email protected]> --- src/northbridge/intel/haswell/gma.c | 3 + src/southbridge/intel/lynxpoint/me_9.x.c | 8 ++- src/southbridge/intel/lynxpoint/pch.c | 11 ++-- src/southbridge/intel/lynxpoint/pch.h | 11 +++- src/southbridge/intel/lynxpoint/sata.c | 35 ++++++++-- src/southbridge/intel/lynxpoint/spi.c | 110 ++++--------------------------- 6 files changed, 70 insertions(+), 108 deletions(-) diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index f791c2b..38fe78a 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -315,14 +315,17 @@ u32 map_oprom_vendev(u32 vendev) case 0x80860402: /* GT1 Desktop */ case 0x80860406: /* GT1 Mobile */ case 0x8086040a: /* GT1 Server */ + case 0x80860a06: /* GT1 ULT */ case 0x80860412: /* GT2 Desktop */ case 0x80860416: /* GT2 Mobile */ case 0x8086041a: /* GT2 Server */ + case 0x80860a16: /* GT2 ULT */ case 0x80860422: /* GT3 Desktop */ case 0x80860426: /* GT3 Mobile */ case 0x8086042a: /* GT3 Server */ + case 0x80860a26: /* GT3 ULT */ new_vendev=0x80860406; /* GT1 Mobile */ break; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index f2e928a..63b5205 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -754,10 +754,16 @@ static struct device_operations device_ops = { .ops_pci = &pci_ops, }; +static const unsigned short pci_device_ids[] = { + 0x8c3a, /* Mobile */ + 0x9c3a, /* Low Power */ + 0 +}; + static const struct pci_driver intel_me __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x8c3a, + .devices= pci_device_ids, }; /****************************************************************************** diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index c4a3acf..e992fb2 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -55,6 +55,12 @@ int pch_silicon_supported(int type, int rev) static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(19, 0): /* Audio DSP */ + RCBA32_OR(FD, PCH_DISABLE_ADSPD); + break; + case PCI_DEVFN(20, 0): /* XHCI */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; @@ -89,9 +95,6 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(29, 0): /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; - case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */ - RCBA32_OR(FD, PCH_DISABLE_P2P); - break; case PCI_DEVFN(31, 0): /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; @@ -101,7 +104,7 @@ static void pch_hide_devfn(unsigned devfn) case PCI_DEVFN(31, 3): /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; - case PCI_DEVFN(31, 5): /* SATA #22 */ + case PCI_DEVFN(31, 5): /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; case PCI_DEVFN(31, 6): /* Thermal Subsystem */ diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index fa8d75f..1de1080 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -403,6 +403,8 @@ unsigned get_gpios(const int *gpio_num_array); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCI 0 /* XHCI Pin */ #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -410,7 +412,11 @@ unsigned get_gpios(const int *gpio_num_array); #define D27IR 0x3148 /* 16bit */ #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ +#define D23IR 0x3158 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ +#define D21IR 0x3164 /* 16bit */ +#define D19IR 0x3168 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -430,8 +436,8 @@ unsigned get_gpios(const int *gpio_num_array); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) -#define PCH_DISABLE_P2P (1 << 1) +#define PCH_DISABLE_ALWAYS (1 << 0) +#define PCH_DISABLE_ADSPD (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) #define PCH_DISABLE_HD_AUDIO (1 << 4) @@ -441,6 +447,7 @@ unsigned get_gpios(const int *gpio_num_array); #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) +#define PCH_DISABLE_XHCI (1 << 27) /* Function Disable 2 RCBA 0x3428 */ #define PCH_DISABLE_KT (1 << 4) diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 81d4a1d..25eb94f 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <delay.h> #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; @@ -123,6 +124,7 @@ static void sata_init(struct device *dev) reg16 &= ~0x3f; reg16 |= 0x8000 | config->sata_port_map; pci_write_config16(dev, 0x92, reg16); + udelay(2); /* Setup register 98h */ reg32 = pci_read_config16(dev, 0x98); @@ -138,6 +140,7 @@ static void sata_init(struct device *dev) #if CONFIG_INTEL_LYNXPOINT_LP reg32 &= ~((1 << 31) | (1 << 30)); reg32 |= 1 << 23; + reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ #endif pci_write_config32(dev, 0x98, reg32); @@ -159,6 +162,9 @@ static void sata_init(struct device *dev) reg32 = read32(abar + 0x00); reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 &= ~0x00020060; // clear SXS+EMS+PMS +#if CONFIG_INTEL_LYNXPOINT_LP + reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY +#endif write32(abar + 0x00, reg32); /* PI (Ports implemented) */ write32(abar + 0x0c, config->sata_port_map); @@ -166,12 +172,13 @@ static void sata_init(struct device *dev) (void) read32(abar + 0x0c); /* Read back 2 */ /* CAP2 (HBA Capabilities Extended)*/ reg32 = read32(abar + 0x24); +#if CONFIG_INTEL_LYNXPOINT_LP + /* Enable DEVSLP */ + reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); +#else reg32 &= ~0x00000002; +#endif write32(abar + 0x24, reg32); - /* VSP (Vendor Specific Register */ - reg32 = read32(abar + 0xa0); - reg32 &= ~0x00000005; - write32(abar + 0xa0, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); @@ -230,15 +237,33 @@ static void sata_init(struct device *dev) /* Additional Programming Requirements */ /* Power Optimizer */ + + /* Step 1 */ +#if CONFIG_INTEL_LYNXPOINT_LP + sir_write(dev, 0x64, 0x883c9003); +#else sir_write(dev, 0x64, 0x883c9001); +#endif + /* Step 2: SIR 68h[15:0] = 880Ah */ reg32 = sir_read(dev, 0x68); reg32 &= 0xffff0000; reg32 |= 0x880a; sir_write(dev, 0x68, reg32); + /* Step 3: SIR 60h[3] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 3); + sir_write(dev, 0x60, reg32); + + /* Step 4: SIR 60h[0] = 1 */ + reg32 = sir_read(dev, 0x60); + reg32 |= (1 << 0); + sir_write(dev, 0x60, reg32); + + /* Step 5: SIR 60h[1] = 1 */ reg32 = sir_read(dev, 0x60); - reg32 |= (1 << 0) | (1 << 1) | (1 << 3); + reg32 |= (1 << 1); sir_write(dev, 0x60, reg32); /* Clock Gating */ diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index ec7c862..123c6a9 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -68,18 +68,6 @@ typedef struct spi_slave ich_spi_slave; static int ichspi_lock = 0; -typedef struct ich7_spi_regs { - uint16_t spis; - uint16_t spic; - uint32_t spia; - uint64_t spid[8]; - uint64_t _pad; - uint32_t bbar; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; -} __attribute__((packed)) ich7_spi_regs; - typedef struct ich9_spi_regs { uint32_t bfpr; uint16_t hsfs; @@ -302,110 +290,40 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return slave; } -/* - * Check if this device ID matches one of supported Intel PCH devices. - * - * Return the ICH version if there is a match, or zero otherwise. - */ -static inline int get_ich_version(uint16_t device_id) -{ - if (device_id >= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN && - device_id <= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX) - return 9; - - return 0; -} - void spi_init(void) { - int ich_version = 0; - uint8_t *rcrb; /* Root Complex Register Block */ uint32_t rcba; /* Root Complex Base Address */ uint8_t bios_cntl; device_t dev; - uint32_t ids; - uint16_t vendor_id, device_id; + ich9_spi_regs *ich9_spi; #ifdef __SMM__ dev = PCI_DEV(0, 31, 0); #else dev = dev_find_slot(0, PCI_DEVFN(31, 0)); #endif - pci_read_config_dword(dev, 0, &ids); - vendor_id = ids; - device_id = (ids >> 16); - - if (vendor_id != PCI_VENDOR_ID_INTEL) { - printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); - return; - } - - ich_version = get_ich_version(device_id); - - if (!ich_version) { - printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); - return; - } pci_read_config_dword(dev, 0xf0, &rcba); /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ rcrb = (uint8_t *)(rcba & 0xffffc000); - switch (ich_version) { - case 7: - { - const uint16_t ich7_spibar_offset = 0x3020; - ich7_spi_regs *ich7_spi = - (ich7_spi_regs *)(rcrb + ich7_spibar_offset); - - ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; - cntlr.opmenu = ich7_spi->opmenu; - cntlr.menubytes = sizeof(ich7_spi->opmenu); - cntlr.optype = &ich7_spi->optype; - cntlr.addr = &ich7_spi->spia; - cntlr.data = (uint8_t *)ich7_spi->spid; - cntlr.databytes = sizeof(ich7_spi->spid); - cntlr.status = (uint8_t *)&ich7_spi->spis; - cntlr.control = &ich7_spi->spic; - cntlr.bbar = &ich7_spi->bbar; - cntlr.preop = &ich7_spi->preop; - break; - } - case 9: - { - const uint16_t ich9_spibar_offset = 0x3800; - ich9_spi_regs *ich9_spi = - (ich9_spi_regs *)(rcrb + ich9_spibar_offset); - ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; - cntlr.opmenu = ich9_spi->opmenu; - cntlr.menubytes = sizeof(ich9_spi->opmenu); - cntlr.optype = &ich9_spi->optype; - cntlr.addr = &ich9_spi->faddr; - cntlr.data = (uint8_t *)ich9_spi->fdata; - cntlr.databytes = sizeof(ich9_spi->fdata); - cntlr.status = &ich9_spi->ssfs; - cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; - cntlr.preop = &ich9_spi->preop; - break; - } - default: - printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); - } - + ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800); + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; ich_set_bbar(0); /* Disable the BIOS write protect so write commands are allowed. */ pci_read_config_byte(dev, 0xdc, &bios_cntl); - switch (ich_version) { - case 9: - /* Deassert SMM BIOS Write Protect Disable. */ - bios_cntl &= ~(1 << 5); - break; - - default: - break; - } + bios_cntl &= ~(1 << 5); pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
