Ronald G. Minnich ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2615
-gerrit commit 8157f987b7d27964a5af99a922044bf146e3f27c Author: Ronald G. Minnich <[email protected]> Date: Fri Mar 8 15:24:44 2013 -0800 samsung/exynos5: add resource functions for the display port Not working, seemingly, but we need to add a 4M resource for memory, and it seems it needs to be fixed at the address shown. This address was chosen from current hardware. Change-Id: Ied65a554f833566be817540702f79a02e7b6cb6e Signed-off-by: Ronald G. Minnich <[email protected]> --- .../exynos5-common/displayport/displayport.c | 35 ++++++++++++++--- src/mainboard/google/snow/devicetree.cb | 44 +++++++++++----------- 2 files changed, 53 insertions(+), 26 deletions(-) diff --git a/src/cpu/samsung/exynos5-common/displayport/displayport.c b/src/cpu/samsung/exynos5-common/displayport/displayport.c index 1c08bc7..e965833 100644 --- a/src/cpu/samsung/exynos5-common/displayport/displayport.c +++ b/src/cpu/samsung/exynos5-common/displayport/displayport.c @@ -83,22 +83,47 @@ static void exynos_displayport_init(void) #endif } -static void exynos_displayport_noop(device_t dummy) +static void exynos_displayport_read_resources(device_t dev) { + struct resource *resource; + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); + /* claim a resource for the UMA graphics. + * Follow the current convention of starting at 24M + * from the start. + */ + resource = new_resource(dev, 0); + resource->base = 0x20000000 + 24*1048576; + resource->size = 1366 * 768 * 4; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + printk(BIOS_DEBUG, "Adding graphics at %p, size %08lx\n", (void *)resource->base, resource->size); +} + +static void exynos_displayport_set_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); +} + +static void exynos_displayport_enable_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s: dev %p\n", __function__, dev); } static struct device_operations exynos_displayport_operations = { - .read_resources = exynos_displayport_noop, - .set_resources = exynos_displayport_noop, - .enable_resources = exynos_displayport_noop, + .read_resources = exynos_displayport_read_resources, + .set_resources = exynos_displayport_set_resources, + .enable_resources = exynos_displayport_enable_resources, .init = exynos_displayport_init, .scan_bus = exynos_displayport_noop, }; static void exynos_displayport_enable(struct device *dev) { - if (dev->link_list != NULL) + printk(BIOS_SPEW, "%s: ", __function__); + if (dev->link_list != NULL){ + printk(BIOS_SPEW, "set ops"); dev->ops = &exynos_displayport_operations; + } + printk(BIOS_SPEW, "\n"); } struct chip_operations drivers_i2c_exynos_displayport_ops = { diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb index 5ad786e..a2b0f62 100644 --- a/src/mainboard/google/snow/devicetree.cb +++ b/src/mainboard/google/snow/devicetree.cb @@ -20,27 +20,29 @@ # FIXME: this is just a stub for now chip cpu/samsung/exynos5250 -device cpu_cluster 0 on -end + device cpu_cluster 0 on + + device domain 0 on + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # ? + device i2c 9 on end # ? + end + chip cpu/samsung/exynos5-common/displayport + register "xres" = "1366" + register "yres" = "768" + register "bpp" = "16" + # complex magic timing! + register "clkval_f" = "2" + register "upper_margin" = "14" + register "lower_margin" = "3" + register "vsync" = "5" + register "left_margin" = "80" + register "right_margin" = "48" + register "hsync" = "32" + register "lcdbase" = "0x10000000" + end + end -device domain 0 on - chip drivers/generic/generic # I2C0 controller - device i2c 6 on end # ? - device i2c 9 on end # ? - end - chip cpu/samsung/exynos5-common/displayport - register "xres" = "1366" - register "yres" = "768" - register "bpp" = "16" - # complex magic timing! - register "clkval_f" = "2" - register "upper_margin" = "14" - register "lower_margin" = "3" - register "vsync" = "5" - register "left_margin" = "80" - register "right_margin" = "48" - register "hsync" = "32" - register "lcdbase" = "0x10000000" end -end + end -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
