* CTO of SPCTNC <[email protected]> [130410 07:31]: > Please help me. > > - How can I fix the problem.
It sounds like you have a RAM init problem (e.g. your RAM is not working) because the chipset (945GC) is slightly different than the other 945 variations that we have supported (just a guess) > - How can I fix gdb problem. GDB right now only works from ramstage, which you don't reach yet. Hence you're out of luck. Try disabling GDB support in coreboot for now. > coreboot-4.0-3784-g1cc4737-dirty Fri Apr 5 22:44:35 BOT 2013 starting... > > Intel(R) 82945GC Chipset > (G)MCH capable of up to DDR2-533 This is odd.. because the boards web page says it can do 667 > Setting up static southbridge registers... GPIOS... done. > Disabling Watchdog reboot... done. > Setting up static northbridge registers... done. > Waiting for MCHBAR to come up...ok > PM1_CNT: 00001c00 > SMBus controller enabled. > Setting up RAM controller. > This mainboard supports Dual Channel Operation. > DDR II Channel 0 Socket 0: x8DDS > DDR II Channel 0 Socket 1: N/A > DDR II Channel 1 Socket 0: N/A > DDR II Channel 1 Socket 1: N/A > lowest common cas = 4 > Probing Speed 2 > DIMM: 0 > Current CAS mask: 0070; idx=1, tCLK=30, tAC=45: OK > DIMM: 1 > DIMM: 2 > DIMM: 3 > freq_cas_mask for speed 2: 0030 > Memory will be driven at 667MHz with CAS=4 clocks So does this... > FSB: 800 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz ... check if 800MHz FSB makes sense.. > Setting Memory Frequency... CLKCFG=0x20000002, CLKCFG=0x20000002, ok > Setting mode of operation for memory channels...Single Channel 0 only. > DCC=0x00000400 > Programming Clock Crossing...MEM=memclk: unknown register value 0 > memclk: unknown register value 0 > RSVD ffffffffSetting RAM size... Definitely something is going wrong with the clock crossing.. you might need a special set of clock crossing values for your chipset.. Looking at the code and the register values with the original bios might help. Look at util/inteltool for a tool to dump those registers. > CBFS: CBFS_HEADER_ROM_ADDRESS: 0xffffefe0/0x80000 > CBFS: CBFS location: 0x0~0x7f000, align: 64 > CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0. > CBFS: - load entry 0x0 file name (16 bytes)... > CBFS: (unmatched file @0x0: cmos_layout.bin) > CBFS: - load entry 0x540 file name (32 bytes)... > CBFS: (unmatched file @0x540: fallback/romstage) > CBFS: - load entry 0xca00 file name (32 bytes)... > CBFS: Found file (offset=0xca38, len=367928). > CBFS: loading stage fallback/coreboot_ram @ 0x100000 (417880 bytes), entry @ > 0x1 > 00000 > CBFS: cbfs_decompress, algo=0, src=fff8ca54, dst=100000, len=367900 > CBFS: src=10f2efa, dst=10f2efa > CBFS: stage loaded. > Jumping to image. This is usually a clear sign that RAM is not working because the code coming after this point would run out of RAM. You can try enabling a more comprehensive ram check here.. Stefan -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
