Dear coreboot folks,
do you know if the timer mentioned in the BIOS and Kernel Developer’s
Guide (BKGD) for the AMD Family 14h processors [1]
2.11.4 BIOS Timer
The root complex implements a 32-bit microsecond timer (see
D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use
to accurately time wait operations between initialization steps.
To ensure that BIOS waits a minimum number of microseconds
between steps BIOS should always wait for one microsecond more
than the required minimum wait time.
could be used for implementing `tsc_freq_mhz()` as done for Intel
Haswell processors?
The Wikipedia article for Time Stamp Counter (TSC) claims that since AMD
family 10h processors a constant TSC is integrated [2]. Indeed, checking
the processor flags under GNU/Linux, the flag `tsc_constant` is present.
$ grep -i tsc /proc/cpuinfo
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor
ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a
misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock
nrip_save pausefilter
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt
pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni monitor
ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a
misalignsse 3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock
nrip_save pausefilter
Suggestions, if this should be shared and how the files should be named
are appreciated.
Thanks,
Paul
[1] http://review.coreboot.org/3169
[2] http://www.coreboot.org/Datasheets#AMD_Fam14
[3]
http://en.wikipedia.org/wiki/Time_Stamp_Counter#Implementation_in_various_processors
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